I forgot, the mem form needs mayLoad=1. Otherwise LGTM.<span></span><br><br>On Thursday, September 12, 2013, Ben Langmuir wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Changes per review:<br>
* FeatureSHA implies FeatureSSE2<br>
* Use i128mem (oops)<br>
* Add sources and constraints for dest registers.<br>
<br>
Hi nadav,<br>
<br>
<a href="http://llvm-reviews.chandlerc.com/D1650" target="_blank">http://llvm-reviews.chandlerc.com/D1650</a><br>
<br>
CHANGE SINCE LAST DIFF<br>
<a href="http://llvm-reviews.chandlerc.com/D1650?vs=4210&id=4227#toc" target="_blank">http://llvm-reviews.chandlerc.com/D1650?vs=4210&id=4227#toc</a><br>
<br>
Files:<br>
lib/Target/X86/X86.td<br>
lib/Target/X86/X86InstrInfo.td<br>
lib/Target/X86/X86InstrSSE.td<br>
lib/Target/X86/X86Subtarget.cpp<br>
lib/Target/X86/X86Subtarget.h<br>
test/MC/Disassembler/X86/x86-64.txt<br>
test/MC/X86/x86_64-encoding.s<br>
<br>
Index: lib/Target/X86/X86.td<br>
===================================================================<br>
--- lib/Target/X86/X86.td<br>
+++ lib/Target/X86/X86.td<br>
@@ -137,6 +137,9 @@<br>
"Support HLE">;<br>
def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",<br>
"Support ADX instructions">;<br>
+def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",<br>
+ "Enable SHA instructions",<br>
+ [FeatureSSE2]>;<br>
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",<br>
"Support PRFCHW instructions">;<br>
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",<br>
Index: lib/Target/X86/X86InstrInfo.td<br>
===================================================================<br>
--- lib/Target/X86/X86InstrInfo.td<br>
+++ lib/Target/X86/X86InstrInfo.td<br>
@@ -675,6 +675,7 @@<br>
def HasHLE : Predicate<"Subtarget->hasHLE()">;<br>
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;<br>
def HasADX : Predicate<"Subtarget->hasADX()">;<br>
+def HasSHA : Predicate<"Subtarget->hasSHA()">;<br>
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;<br>
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;<br>
def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;<br>
Index: lib/Target/X86/X86InstrSSE.td<br>
===================================================================<br>
--- lib/Target/X86/X86InstrSSE.td<br>
+++ lib/Target/X86/X86InstrSSE.td<br>
@@ -7309,6 +7309,21 @@<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
+// SHA-NI Instructions<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+let Constraints = "$src1 = $dst", hasSideEffects = 0, Predicates = [HasSHA] in {<br>
+ def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),<br>
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),<br>
+ "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
+ []>, TA;<br>
+ def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),<br>
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),<br>
+ "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
+ []>, TA;<br>
+}<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
// AES-NI Instructions<br>
//===----------------------------------------------------------------------===//<br>
<br>
Index: lib/Target/X86/X86Subtarget.cpp<br>
===================================================================<br>
--- lib/Target/X86/X86Subtarget.cpp<br>
+++ lib/Target/X86/X86Subtarget.cpp<br>
@@ -375,6 +375,10 @@<br>
HasCDI = true;<br>
ToggleFeature(X86::FeatureCDI);<br>
}<br>
+ if (IsIntel && ((EBX >> 29) & 0x1)) {<br>
+ HasSHA = true;<br>
+ ToggleFeature(X86::FeatureSHA);<br>
+ }<br>
}<br>
}<br>
}<br>
@@ -497,6 +501,7 @@<br>
HasCDI = false;<br>
HasPFI = false;<br>
HasADX = false;<br>
+ HasSHA = false;<br>
HasPRFCHW = false;<br>
HasRDSEED = false;<br>
IsBTMemSlow = false;<br>
Index: lib/Target/X86/X86Subtarget.h<br>
===================================================================<br>
--- lib/Target/X86/X86Subtarget.h<br>
+++ lib/Target/X86/X86Subtarget.h<br>
@@ -127,6 +127,9 @@<br>
/// HasADX - Processor has ADX instructions.<br>
bool HasADX;<br>
<br>
+ /// HasSHA - Processor has SHA instructions.<br>
+ bool HasSHA;<br>
+<br>
/// HasPRFCHW - Processor has PRFCHW instructions.<br>
bool HasPRFCHW;<br>
<br>
@@ -281,6 +284,7 @@<br>
bool hasRTM() const { return HasRTM; }<br>
bool hasHLE() const { return HasHLE; }<br>
bool hasADX() const { return HasADX; }<br>
+ bool hasSHA() const { return HasSHA; }<br>
bool hasPRFCHW() const { return HasPRFCHW; }<br>
bool hasRDSEED() const { return HasRDSEED; }<br>
bool isBTMemSlow() const { return IsBTMemSlow; }<br>
Index: test/MC/Disassembler/X86/x86-64.txt<br>
===================================================================<br>
--- test/MC/Disassembler/X86/x86-64.txt<br>
+++ test/MC/Disassembler/X86/x86-64.txt<br>
@@ -157,3 +157,9 @@<br>
<br>
# CHECK: movabsq %rax, -6066930261531658096<br>
0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab<br>
+<br>
+# CHECK: sha1rnds4 $1, %xmm1, %xmm2<br>
+0x0f 0x3a 0xcc 0xd1 0x01<br>
+<br>
+# CHECK: sha1rnds4 $1, (%rax), %xmm2<br>
+0x0f 0x3a 0xcc 0x10 0x01<br>
\ No newline at end of file<br>
Index: test/MC/X86/x86_64-encoding.s<br>
===================================================================<br>
--- test/MC/X86/x86_64-encoding.s<br>
+++ test/MC/X86/x86_64-encoding.s<br>
@@ -120,6 +120,14 @@<br>
// CHECK: fixup A - offset: 5, value: CPI1_0-4<br>
pshufb CPI1_0(%rip), %xmm1<br>
<br>
+// CHECK: sha1rnds4 $1, %xmm1, %xmm2<br>
+// CHECK: encoding: [0x0f,0x3a,0xcc,0xd1,0x01]<br>
+sha1rnds4 $1, %xmm1, %xmm2<br>
+<br>
+// CHECK: sha1rnds4 $1, (%rax), %xmm2<br>
+// CHECK: encoding: [0x0f,0x3a,0xcc,0x10,0x01]<br>
+sha1rnds4 $1, (%rax), %xmm2<br>
+<br>
// CHECK: movq 57005(,%riz), %rbx<br>
// CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]<br>
movq 57005(,%riz), %rbx<br>
</blockquote><br><br>-- <br>~Craig<br>