<div dir="ltr">On Tue, Sep 10, 2013 at 4:18 PM, Eli Friedman <span dir="ltr"><<a href="mailto:eli.friedman@gmail.com" target="_blank">eli.friedman@gmail.com</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote">
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: efriedma<br>
Date: Tue Sep 10 18:18:14 2013<br>
New Revision: 190448<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=190448&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=190448&view=rev</a><br>
Log:<br>
Fix unused variables.<br>
<br>
Modified:<br>
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
    llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp<br>
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
    llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp<br>
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=190448&r1=190447&r2=190448&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=190448&r1=190447&r2=190448&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Sep 10 18:18:14 2013<br>
@@ -120,7 +120,9 @@ class RAGreedy : public MachineFunctionP<br>
     RS_Done<br>
   };<br>
<br>
+#ifndef NDEBUG<br>
   static const char *const StageName[];<br>
+#endif<br>
<br>
   // RegInfo - Keep additional information about each live range.<br>
   struct RegInfo {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=190448&r1=190447&r2=190448&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=190448&r1=190447&r2=190448&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Tue Sep 10 18:18:14 2013<br>
@@ -389,7 +389,6 @@ signed ResourcePriorityQueue::regPressur<br>
 // Constants used to denote relative importance of<br>
 // heuristic components for cost computation.<br>
 static const unsigned PriorityOne = 200;<br>
-static const unsigned PriorityTwo = 100;<br>
 static const unsigned PriorityThree = 50;<br>
 static const unsigned PriorityFour = 15;<br>
 static const unsigned PriorityFive = 5;<br></blockquote><div><br></div><div>The resulting code here looks a bit weird, due to the discontiguous priorities. Can we rename these or something?</div><div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=190448&r1=190447&r2=190448&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=190448&r1=190447&r2=190448&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Sep 10 18:18:14 2013<br>
@@ -39,8 +39,6 @@<br>
<br>
 using namespace llvm;<br>
<br>
-const unsigned Hexagon_MAX_RET_SIZE = 64;<br>
-<br>
 static cl::opt<bool><br>
 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,<br>
                cl::desc("Control jump table emission on Hexagon target"));<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=190448&r1=190447&r2=190448&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=190448&r1=190447&r2=190448&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Tue Sep 10 18:18:14 2013<br>
@@ -457,9 +457,7 @@ static SUnit *getSingleUnscheduledSucc(S<br>
 // Constants used to denote relative importance of<br>
 // heuristic components for cost computation.<br>
 static const unsigned PriorityOne = 200;<br>
-static const unsigned PriorityTwo = 100;<br>
 static const unsigned PriorityThree = 50;<br>
-static const unsigned PriorityFour = 20;<br>
 static const unsigned ScaleTwo = 10;<br>
 static const unsigned FactorOne = 2;</blockquote><div><br></div><div>Here too. </div><div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=190448&r1=190447&r2=190448&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=190448&r1=190447&r2=190448&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Sep 10 18:18:14 2013<br>
@@ -2224,8 +2224,6 @@ static bool CC_MipsO32_FP64(unsigned Val<br>
 //                  Call Calling Convention Implementation<br>
 //===----------------------------------------------------------------------===//<br>
<br>
-static const unsigned O32IntRegsSize = 4;<br>
-<br>
 // Return next O32 integer argument register.<br>
 static unsigned getNextIntArgReg(unsigned Reg) {<br>
   assert((Reg == Mips::A0) || (Reg == Mips::A2));<br>
<br>
<br>
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</blockquote></div><br></div></div>