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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Great! Thanks for your help. Committed as r189958.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">- Silviu<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Andrew Trick [mailto:atrick@apple.com]
<br>
<b>Sent:</b> 04 September 2013 17:22<br>
<b>To:</b> Silviu Baranga<br>
<b>Cc:</b> Arnold Schwaighofer; llvm commits; Renato Golin<br>
<b>Subject:</b> Re: [PATCH] Add Cortex-A9 scheduling classes for vldm/vstm instructions that access more than 32 bytes<o:p></o:p></span></p>
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<p class="MsoNormal">On Sep 4, 2013, at 6:46 AM, Silviu Baranga <<a href="mailto:Silviu.Baranga@arm.com">Silviu.Baranga@arm.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Andy,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks for that great description! The explanation makes sense and I would like to a stab at this (patch attached).</span><o:p></o:p></p>
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<p class="MsoNormal">That looks great. Please commit. And thanks a lot!<o:p></o:p></p>
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<p class="MsoNormal">-Andy<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">If it’s completely wrong, I’ll hand it over to you.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Silviu</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span class="apple-converted-space"><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> </span></span><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Andrew
Trick [<a href="mailto:atrick@apple.com"><span style="color:purple">mailto:atrick@apple.com</span></a>]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>04 September 2013 02:04<br>
<b>To:</b><span class="apple-converted-space"> </span>Silviu Baranga<br>
<b>Cc:</b><span class="apple-converted-space"> </span>Arnold Schwaighofer; llvm commits; Renato Golin<br>
<b>Subject:</b><span class="apple-converted-space"> </span>Re: [PATCH] Add Cortex-A9 scheduling classes for vldm/vstm instructions that access more than 32 bytes</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">On Sep 3, 2013, at 2:02 AM, Silviu Baranga <<a href="mailto:Silviu.Baranga@arm.com"><span style="color:purple">Silviu.Baranga@arm.com</span></a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">That was a dumb mistake.. Should be fixed now. Is it OK to commit?<br>
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@Renato: thanks for your help progressing this!</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Hi Silviu,<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">I apologize for missing this when you first sent it. Thanks, Renato for getting on my case.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">I really appreciate that you provided a test case and improved tablegen syntax using A9WriteLMOpsListType and sequence ranges. I know this particular problem has been spotted before but we must have forgotten to fix it. When I wrote this
part of the A9 model, I expected getNumLDMAddresses() to return 8 for 64-byte VLDM (each address loads 64-bits)--hence the assert that you see. Now it actually returns 16 (for 32-bit loads). Unfortunately your patch is propagating the bug to the extent that
we no longer notice it. Changing getNumLDMAddresses() again is probably not worth doing, given that it's properly implemented for Swift, but it shouldn't be hard to fix the A9 machine model. Let me explain how it works:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">The LDM machine model is a nightmare for a few reasons. Mainly because the PostRA form of the instruction was never ported to the new register tuple framework. Partly because we have no good way of determining the size of the load. Partly
because the machine model simultaneously handles LDM and VLDM, S and D register form, and resource and latency. Let me explain how it works:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Looking at the PostRA form, which is what you're concerned with:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span>VLDMDIA %SP, pred:14, pred:%noreg, %D16<def>, %D17<def>, %D18<def>, %D19<def>, %D20<def>, %D21<def>, %D22<def>, %D23<def>, %Q8_Q9_Q10_Q11<imp-def>;
mem:LD64<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">The machine model dictates that we define a list of SchedWrite types at least as long as the list of explicit def operands (>= 8). Ideally we have:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">def A9WriteLMfpPostRA : SchedWriteVariant<[<o:p></o:p></p>
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<p class="MsoNormal">...<o:p></o:p></p>
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<p class="MsoNormal"> SchedVar<A9LMAdr16Pred, [A9WriteLMfp1,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp2,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp3,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp4,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp5,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp6,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp7,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp8]>,<o:p></o:p></p>
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<p class="MsoNormal">...<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Where the latency of each A9WriteLMfp#N is N cycles, and the total instruction resources are the sum of each def's resources: 8 LoadStore units and 8 FP units.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Now, 64-byte VLDM could in theory contain 16 S-register defs. We want to allow the machine model handle this case, but don't really care about the accuracy. We can just reuse the same 8 D-register scheduling class as such:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"> SchedVar<A9LMAdr16Pred, [A9WriteLMfp1,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp2,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp3,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp4,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp5,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp6,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp7,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp8,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp5Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp5Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp6Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp6Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp7Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp7Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp8Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp8Hi]>,<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">The SchedWrite types with "Hi" suffix do not take any processor resources. They only convey the latency to the register def operand at that position--in the D register case they won't have any effect. The first four odd-number S registers
have an extra cycle of latency at the cost of reusing the model. You could express a perfect model, but would need even more predicates.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Another way to cut the number of scheduling classes in half is to notice that the number of resources used are the same for even/odd LDM/VLDM pairs.<o:p></o:p></p>
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<p class="MsoNormal">def A9LMAdr#NumAddr#Pred :<o:p></o:p></p>
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<p class="MsoNormal"> SchedPredicate<"(TII->getNumLDMAddresses(MI)+1)/2 == "#NumAddr>;<o:p></o:p></p>
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<p class="MsoNormal">...<o:p></o:p></p>
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<p class="MsoNormal"> SchedVar<A9LMAdr1Pred, [A9WriteLMfp1,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp1Hi]>,<o:p></o:p></p>
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<p class="MsoNormal"> SchedVar<A9LMAdr2Pred, [A9WriteLMfp1,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp2,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp2Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp2Hi]>,<o:p></o:p></p>
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<p class="MsoNormal"> SchedVar<A9LMAdr3Pred, [A9WriteLMfp1,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp2,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp3,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp2Hi,<o:p></o:p></p>
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<p class="MsoNormal"> A9WriteLMfp3Hi,<o:p></o:p></p>
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<p class="MsoNormal"><span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> <span class="apple-tab-span"> </span><span class="apple-converted-space"> </span> A9WriteLMfp3Hi]>,<o:p></o:p></p>
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<p class="MsoNormal">...<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Then you're back to only 8 predicates, with A9LMAdr8Pred covering your 64-byte case (which is what I originally intended). The only difference from the current model is the fix to the NumLDMAddresses predicate, and to optimize for the D-register
case, not the S-register case (plus test case and tablegen niceness that you added).<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">If my explanation actually makes sense to you, please take a crack at fixing it this way. Otherwise, feel free to hand it off to me.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">-Andy<o:p></o:p></p>
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</span><span style="font-size:10.0pt;font-family:"Arial","sans-serif"">-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately
and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.<br>
<br>
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590<br>
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782<br>
</span><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><A9SchedLDM.diff><o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<br>
<font face="Arial" color="Black" size="2">-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.<br>
<br>
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590<br>
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782<br>
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