<div dir="ltr">I'm not entirely convinced the same bug isn't in the MCJIT. Or MCJIT has fixed this a different way.</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Aug 20, 2013 at 10:03 PM, Nadav Rotem <span dir="ltr"><<a href="mailto:nrotem@apple.com" target="_blank">nrotem@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: nadav<br>
Date: Wed Aug 21 00:03:10 2013<br>
New Revision: 188866<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=188866&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=188866&view=rev</a><br>
Log:<br>
In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.<br>
<br>
Patch by Chris Bieneman.<br>
<br>
<br>
Added:<br>
    llvm/trunk/test/ExecutionEngine/fma3-jit.ll<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=188866&r1=188865&r2=188866&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=188866&r1=188865&r2=188866&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Aug 21 00:03:10 2013<br>
@@ -985,8 +985,14 @@ void Emitter<CodeEmitter>::emitVEXOpcode<br>
       if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))<br>
         VEX_R = 0x0;<br>
<br>
-      if (HasVEX_4V)<br>
-        VEX_4V = getVEXRegisterEncoding(MI, 1);<br>
+      if (HasVEX_4V) {<br>
+        if (HasMemOp4)<br>
+          VEX_4V = getVEXRegisterEncoding(MI, 1);<br>
+        else<br>
+          // FMA3 instructions operands are dst, src1, src2, src3<br>
+          // dst and src1 are the same and not encoded separately<br>
+          VEX_4V = getVEXRegisterEncoding(MI, 2);<br>
+      }<br>
<br>
       if (X86II::isX86_64ExtendedReg(<br>
                           MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))<br>
<br>
Added: llvm/trunk/test/ExecutionEngine/fma3-jit.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/fma3-jit.ll?rev=188866&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/fma3-jit.ll?rev=188866&view=auto</a><br>

==============================================================================<br>
--- llvm/trunk/test/ExecutionEngine/fma3-jit.ll (added)<br>
+++ llvm/trunk/test/ExecutionEngine/fma3-jit.ll Wed Aug 21 00:03:10 2013<br>
@@ -0,0 +1,18 @@<br>
+; RUN: %lli %s | FileCheck %s<br>
+; REQUIRES: fma3<br>
+; CHECK: 12.000000<br>
+<br>
+@msg_double = internal global [4 x i8] c"%f\0A\00"<br>
+<br>
+declare i32 @printf(i8*, ...)<br>
+<br>
+define i32 @main() {<br>
+  %fma = tail call double @llvm.fma.f64(double 3.0, double 3.0, double 3.0) nounwind readnone<br>
+<br>
+  %ptr1 = getelementptr [4 x i8]* @msg_double, i32 0, i32 0<br>
+  call i32 (i8*,...)* @printf(i8* %ptr1, double %fma)<br>
+<br>
+  ret i32 0<br>
+}<br>
+<br>
+declare double @llvm.fma.f64(double, double, double) nounwind readnone<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br>~Craig
</div>