<div dir="ltr">Hi Tom!<div><br></div><div>This commit breaks our ASan bootstrap bot.</div><div>The test</div><div> LLVM :: CodeGen/R600/indirect-addressing-si.ll<br></div><div>fails with the following report:</div><div><div>
=================================================================</div><div>==5720==ERROR: AddressSanitizer: global-buffer-overflow on address 0x000002f35010 at pc 0xf0a316 bp 0x7fff36b19a90 sp 0x7fff36b19a88</div><div>READ of size 2 at 0x000002f35010 thread T0</div>
<div> #0 0xf0a315 in (anonymous namespace)::AMDGPUDAGToDAGISel::getOperandRegClass(llvm::SDNode*, unsigned int) const llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp:118</div><div> #1 0xf04780 in (anonymous namespace)::AMDGPUDAGToDAGISel::CheckNodePredicate(llvm::SDNode*, unsigned int) const llvm_build_asan/lib/Target/R600/AMDGPUGenDAGISel.inc:14035</div>
<div> #2 0x191500a in llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1976</div><div> #3 0xeff4eb in SelectCode llvm_build_asan/lib/Target/R600/AMDGPUGenDAGISel.inc:13723</div>
<div> #4 0xeff4eb in (anonymous namespace)::AMDGPUDAGToDAGISel::Select(llvm::SDNode*) llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp:496</div><div> #5 0x1906f07 in llvm::SelectionDAGISel::DoInstructionSelection() llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:790</div>
<div> #6 0x1903823 in llvm::SelectionDAGISel::CodeGenAndEmitDAG() llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:691</div><div> #7 0x18fefad in llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1134</div>
<div> #8 0x18f898e in llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:387</div><div> #9 0x1e3c1cb in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) llvm/lib/CodeGen/MachineFunctionPass.cpp:33</div>
<div> #10 0x279c42c in llvm::FPPassManager::runOnFunction(llvm::Function&) llvm/lib/IR/PassManager.cpp:1530</div><div> #11 0x279c9f5 in llvm::FPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/PassManager.cpp:1550</div>
<div> #12 0x279d21b in llvm::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/PassManager.cpp:1608</div><div> #13 0x279e433 in llvm::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/PassManager.cpp:1703</div>
<div> #14 0x53351f in compileModule llvm/tools/llc/llc.cpp:376</div><div> #15 0x53351f in main llvm/tools/llc/llc.cpp:197</div><div> #16 0x7fee21eb276c in __libc_start_main /build/buildd/eglibc-2.15/csu/libc-start.c:226</div>
<div> #17 0x52effc in _start (llvm_build_asan/bin/llc+0x52effc)</div><div>0x000002f35010 is located 48 bytes to the left of global variable 'llvm::OperandInfo69' from 'llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp' (0x2f35040) of size 48</div>
<div>0x000002f35010 is located 0 bytes to the right of global variable 'llvm::OperandInfo68' from 'llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp' (0x2f34fe0) of size 48</div><div>SUMMARY: AddressSanitizer: global-buffer-overflow llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp:118 (anonymous namespace)::AMDGPUDAGToDAGISel::getOperandRegClass(llvm::SDNode*, unsigned int) const</div>
</div><div><br></div><div><br></div><div>I've commited a tentative fix to bring the bot back in r188448. Not sure if the fix is correct - probably you should fix the caller and add an assert to getOperandRegClass function.</div>
<div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, Aug 15, 2013 at 3:24 AM, Tom Stellard <span dir="ltr"><<a href="mailto:thomas.stellard@amd.com" target="_blank">thomas.stellard@amd.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: tstellar<br>
Date: Wed Aug 14 18:24:24 2013<br>
New Revision: 188426<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=188426&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=188426&view=rev</a><br>
Log:<br>
R600/SI: Choose the correct MOV instruction for copying immediates<br>
<br>
The instruction selector will now try to infer the destination register<br>
so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying<br>
immediates.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/R600/SIInstrInfo.td<br>
llvm/trunk/lib/Target/R600/SIInstructions.td<br>
llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp<br>
llvm/trunk/lib/Target/R600/SIRegisterInfo.h<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp?rev=188426&r1=188425&r2=188426&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp?rev=188426&r1=188425&r2=188426&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp Wed Aug 14 18:24:24 2013<br>
@@ -77,6 +77,7 @@ private:<br>
bool isLocalLoad(const LoadSDNode *N) const;<br>
bool isRegionLoad(const LoadSDNode *N) const;<br>
<br>
+ const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;<br>
bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);<br>
bool SelectGlobalValueVariableOffset(SDValue Addr,<br>
SDValue &BaseReg, SDValue& Offset);<br>
@@ -102,6 +103,34 @@ AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(T<br>
AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {<br>
}<br>
<br>
+/// \brief Determine the register class for \p OpNo<br>
+/// \returns The register class of the virtual register that will be used for<br>
+/// the given operand number \OpNo or NULL if the register class cannot be<br>
+/// determined.<br>
+const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,<br>
+ unsigned OpNo) const {<br>
+ if (!N->isMachineOpcode()) {<br>
+ return NULL;<br>
+ }<br>
+ switch (N->getMachineOpcode()) {<br>
+ default: {<br>
+ const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());<br>
+ int RegClass = Desc.OpInfo[Desc.getNumDefs() + OpNo].RegClass;<br>
+ if (RegClass == -1) {<br>
+ return NULL;<br>
+ }<br>
+ return TM.getRegisterInfo()->getRegClass(RegClass);<br>
+ }<br>
+ case AMDGPU::REG_SEQUENCE: {<br>
+ const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(<br>
+ cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());<br>
+ unsigned SubRegIdx =<br>
+ dyn_cast<ConstantSDNode>(N->getOperand(OpNo + 1))->getZExtValue();<br>
+ return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);<br>
+ }<br>
+ }<br>
+}<br>
+<br>
SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {<br>
return CurDAG->getTargetConstant(Imm, MVT::i32);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=188426&r1=188425&r2=188426&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=188426&r1=188425&r2=188426&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Wed Aug 14 18:24:24 2013<br>
@@ -58,6 +58,22 @@ class InlineImm <ValueType vt> : PatLeaf<br>
(*(const SITargetLowering *)getTargetLowering()).analyzeImmediate(N) == 0;<br>
}]>;<br>
<br>
+class SGPRImm <dag frag> : PatLeaf<frag, [{<br>
+ if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <<br>
+ AMDGPUSubtarget::SOUTHERN_ISLANDS) {<br>
+ return false;<br>
+ }<br>
+ const SIRegisterInfo *SIRI =<br>
+ static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());<br>
+ for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();<br>
+ U != E; ++U) {<br>
+ if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {<br>
+ return true;<br>
+ }<br>
+ }<br>
+ return false;<br>
+}]>;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// SI assembler operands<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=188426&r1=188425&r2=188426&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=188426&r1=188425&r2=188426&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Wed Aug 14 18:24:24 2013<br>
@@ -1583,6 +1583,16 @@ def : Pat <<br>
/********** ================== **********/<br>
<br>
def : Pat <<br>
+ (SGPRImm<(i32 imm)>:$imm),<br>
+ (S_MOV_B32 imm:$imm)<br>
+>;<br>
+<br>
+def : Pat <<br>
+ (SGPRImm<(f32 fpimm)>:$imm),<br>
+ (S_MOV_B32 fpimm:$imm)<br>
+>;<br>
+<br>
+def : Pat <<br>
(i32 imm:$imm),<br>
(V_MOV_B32_e32 imm:$imm)<br>
>;<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp?rev=188426&r1=188425&r2=188426&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp?rev=188426&r1=188425&r2=188426&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp Wed Aug 14 18:24:24 2013<br>
@@ -70,3 +70,14 @@ const TargetRegisterClass *SIRegisterInf<br>
}<br>
return NULL;<br>
}<br>
+<br>
+bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {<br>
+ if (!RC) {<br>
+ return false;<br>
+ }<br>
+ return RC == &AMDGPU::SReg_32RegClass ||<br>
+ RC == &AMDGPU::SReg_64RegClass ||<br>
+ RC == &AMDGPU::SReg_128RegClass ||<br>
+ RC == &AMDGPU::SReg_256RegClass ||<br>
+ RC == &AMDGPU::SReg_512RegClass;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.h?rev=188426&r1=188425&r2=188426&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.h?rev=188426&r1=188425&r2=188426&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.h (original)<br>
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.h Wed Aug 14 18:24:24 2013<br>
@@ -45,6 +45,9 @@ struct SIRegisterInfo : public AMDGPUReg<br>
/// \brief Return the 'base' register class for this register.<br>
/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.<br>
const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;<br>
+<br>
+ /// \returns true if this class contains only SGPR registers<br>
+ bool isSGPRClass(const TargetRegisterClass *RC) const;<br>
};<br>
<br>
} // End namespace llvm<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Alexey Samsonov, MSK</div>
</div></div>