<div dir="ltr">Hi Tom,<div><br></div><div>The test in test/CodeGen/SI doesn't actually get run currently, because there is no lit.local.cfg which enables its suffix. I am about to fix this problem globally, but this test crashes now on my machine:</div>
<div>--</div><div><div>-- Testing: 1 tests, 1 threads --</div><div>Testing: 0 .. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. </div><div>FAIL: LLVM :: CodeGen/SI/sanity.ll (1 of 1)</div><div>******************** TEST 'LLVM :: CodeGen/SI/sanity.ll' FAILED ********************</div>
<div>Script:</div><div>--</div><div>/Volumes/OzzyData/Users/ddunbar/llvm.obj.64/Debug+Asserts/bin/llc < /Volumes/OzzyData/Users/ddunbar/llvm/test/CodeGen/SI/sanity.ll -march=r600 -mcpu=SI | /Volumes/OzzyData/Users/ddunbar/llvm.obj.64/Debug+Asserts/bin/FileCheck /Volumes/OzzyData/Users/ddunbar/llvm/test/CodeGen/SI/sanity.ll</div>
<div>--</div><div>Exit Code: 2</div><div><br></div><div>Command Output (stderr):</div><div>--</div><div>0x7fe0f1034210: i64 = GlobalAddress<void (i32)* @llvm.AMDGPU.shader.type> 0 [ORD=1]</div><div>Undefined function</div>
<div>UNREACHABLE executed at /Volumes/OzzyData/Users/ddunbar/llvm/lib/Target/R600/AMDGPUISelLowering.h:68!</div><div>0 llc 0x00000001091b9dfe llvm::sys::PrintStackTrace(__sFILE*) + 46</div><div>1 llc 0x00000001091ba10b PrintStackTraceSignalHandler(void*) + 27</div>
<div>2 llc 0x00000001091ba488 SignalHandler(int) + 408</div><div>3 libsystem_platform.dylib 0x00007fff94c095aa _sigtramp + 26</div><div>4 llc 0x00000001096ff2df guard variable for llvm::system_category()::s + 621559</div>
<div>5 llc 0x00000001091ba13b raise + 27</div><div>6 llc 0x00000001091ba1f2 abort + 18</div><div>7 llc 0x0000000109198b86 llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 198</div>
<div>8 llc 0x0000000107ec23ff llvm::AMDGPUTargetLowering::LowerCall(llvm::TargetLowering::CallLoweringInfo&, llvm::SmallVectorImpl<llvm::SDValue>&) const + 63</div><div>9 llc 0x00000001087af8f2 llvm::TargetLowering::LowerCallTo(llvm::TargetLowering::CallLoweringInfo&) const + 4146</div>
<div>10 llc 0x0000000108794176 llvm::SelectionDAGBuilder::LowerCallTo(llvm::ImmutableCallSite, llvm::SDValue, bool, llvm::MachineBasicBlock*) + 3494</div><div>11 llc 0x0000000108782105 llvm::SelectionDAGBuilder::visitCall(llvm::CallInst const&) + 2549</div>
<div>12 llc 0x0000000108779a49 llvm::SelectionDAGBuilder::visit(unsigned int, llvm::User const&) + 1097</div><div>13 llc 0x0000000108778ce3 llvm::SelectionDAGBuilder::visit(llvm::Instruction const&) + 131</div>
<div>14 llc 0x00000001087e876c llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 140</div>
<div>15 llc 0x00000001087e8556 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 4214</div><div>16 llc 0x00000001087e65a4 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1108</div>
<div>17 llc 0x0000000108a148be llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 110</div><div>18 llc 0x00000001090f578f llvm::FPPassManager::runOnFunction(llvm::Function&) + 431</div>
<div>19 llc 0x00000001090f5a78 llvm::FPPassManager::runOnModule(llvm::Module&) + 104</div><div>20 llc 0x00000001090f6146 llvm::MPPassManager::runOnModule(llvm::Module&) + 1350</div>
<div>21 llc 0x00000001090f6c0e llvm::PassManagerImpl::run(llvm::Module&) + 302</div><div>22 llc 0x00000001090f6ea1 llvm::PassManager::run(llvm::Module&) + 33</div><div>23 llc 0x0000000107da8db9 compileModule(char**, llvm::LLVMContext&) + 6185</div>
<div>24 llc 0x0000000107da7522 main + 226</div><div>25 libdyld.dylib 0x00007fff932d15fd start + 1</div><div>26 libdyld.dylib 0x0000000000000003 start + 1825761799</div><div>Stack dump:</div>
<div>0.<span class="" style="white-space:pre"> </span>Program arguments: /Volumes/OzzyData/Users/ddunbar/llvm.obj.64/Debug+Asserts/bin/llc -march=r600 -mcpu=SI </div><div>1.<span class="" style="white-space:pre"> </span>Running pass 'Function Pass Manager' on module '<stdin>'.</div>
<div>2.<span class="" style="white-space:pre"> </span>Running pass 'AMDGPU DAG->DAG Pattern Instruction Selection' on function '@main'</div><div>FileCheck error: '-' is empty.</div><div><br></div>
<div>--</div><div><br></div><div>********************</div><div>Testing Time: 12.76s</div><div>********************</div><div>Failing Tests (1):</div><div> LLVM :: CodeGen/SI/sanity.ll</div><div><br></div><div> Unexpected Failures: 1</div>
</div><div>--</div><div><br></div><div>I will XFAIL it for the time being, but could you take a look?</div><div><br></div><div>Thanks,</div><div> - Daniel</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">
On Tue, Dec 11, 2012 at 1:25 PM, Tom Stellard <span dir="ltr"><<a href="mailto:thomas.stellard@amd.com" target="_blank">thomas.stellard@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: tstellar<br>
Date: Tue Dec 11 15:25:42 2012<br>
New Revision: 169915<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=169915&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=169915&view=rev</a><br>
Log:<br>
Add R600 backend<br>
<br>
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX<br>
<br>
Added:<br>
llvm/trunk/include/llvm/IntrinsicsR600.td<br>
llvm/trunk/lib/Target/R600/<br>
llvm/trunk/lib/Target/R600/AMDGPU.h<br>
llvm/trunk/lib/Target/R600/AMDGPU.td<br>
llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h<br>
llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h<br>
llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h<br>
llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h<br>
llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td<br>
llvm/trunk/lib/Target/R600/AMDGPUInstructions.td<br>
llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td<br>
llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h<br>
llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h<br>
llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td<br>
llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h<br>
llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h<br>
llvm/trunk/lib/Target/R600/AMDIL.h<br>
llvm/trunk/lib/Target/R600/AMDIL7XXDevice.cpp<br>
llvm/trunk/lib/Target/R600/AMDIL7XXDevice.h<br>
llvm/trunk/lib/Target/R600/AMDILBase.td<br>
llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp<br>
llvm/trunk/lib/Target/R600/AMDILDevice.cpp<br>
llvm/trunk/lib/Target/R600/AMDILDevice.h<br>
llvm/trunk/lib/Target/R600/AMDILDeviceInfo.cpp<br>
llvm/trunk/lib/Target/R600/AMDILDeviceInfo.h<br>
llvm/trunk/lib/Target/R600/AMDILDevices.h<br>
llvm/trunk/lib/Target/R600/AMDILEvergreenDevice.cpp<br>
llvm/trunk/lib/Target/R600/AMDILEvergreenDevice.h<br>
llvm/trunk/lib/Target/R600/AMDILFrameLowering.cpp<br>
llvm/trunk/lib/Target/R600/AMDILFrameLowering.h<br>
llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/AMDILInstrInfo.td<br>
llvm/trunk/lib/Target/R600/AMDILIntrinsicInfo.cpp<br>
llvm/trunk/lib/Target/R600/AMDILIntrinsicInfo.h<br>
llvm/trunk/lib/Target/R600/AMDILIntrinsics.td<br>
llvm/trunk/lib/Target/R600/AMDILNIDevice.cpp<br>
llvm/trunk/lib/Target/R600/AMDILNIDevice.h<br>
llvm/trunk/lib/Target/R600/AMDILPeepholeOptimizer.cpp<br>
llvm/trunk/lib/Target/R600/AMDILRegisterInfo.td<br>
llvm/trunk/lib/Target/R600/AMDILSIDevice.cpp<br>
llvm/trunk/lib/Target/R600/AMDILSIDevice.h<br>
llvm/trunk/lib/Target/R600/CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/InstPrinter/<br>
llvm/trunk/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp<br>
llvm/trunk/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h<br>
llvm/trunk/lib/Target/R600/InstPrinter/CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/InstPrinter/LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/InstPrinter/Makefile<br>
llvm/trunk/lib/Target/R600/LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.cpp<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/Makefile<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/R600/Makefile<br>
llvm/trunk/lib/Target/R600/Processors.td<br>
llvm/trunk/lib/Target/R600/R600Defines.h<br>
llvm/trunk/lib/Target/R600/R600ExpandSpecialInstrs.cpp<br>
llvm/trunk/lib/Target/R600/R600ISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/R600ISelLowering.h<br>
llvm/trunk/lib/Target/R600/R600InstrInfo.cpp<br>
llvm/trunk/lib/Target/R600/R600InstrInfo.h<br>
llvm/trunk/lib/Target/R600/R600Instructions.td<br>
llvm/trunk/lib/Target/R600/R600Intrinsics.td<br>
llvm/trunk/lib/Target/R600/R600MachineFunctionInfo.cpp<br>
llvm/trunk/lib/Target/R600/R600MachineFunctionInfo.h<br>
llvm/trunk/lib/Target/R600/R600RegisterInfo.cpp<br>
llvm/trunk/lib/Target/R600/R600RegisterInfo.h<br>
llvm/trunk/lib/Target/R600/R600RegisterInfo.td<br>
llvm/trunk/lib/Target/R600/R600Schedule.td<br>
llvm/trunk/lib/Target/R600/SIAssignInterpRegs.cpp<br>
llvm/trunk/lib/Target/R600/SIFixSGPRLiveness.cpp<br>
llvm/trunk/lib/Target/R600/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/SIISelLowering.h<br>
llvm/trunk/lib/Target/R600/SIInstrFormats.td<br>
llvm/trunk/lib/Target/R600/SIInstrInfo.cpp<br>
llvm/trunk/lib/Target/R600/SIInstrInfo.h<br>
llvm/trunk/lib/Target/R600/SIInstrInfo.td<br>
llvm/trunk/lib/Target/R600/SIInstructions.td<br>
llvm/trunk/lib/Target/R600/SIIntrinsics.td<br>
llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp<br>
llvm/trunk/lib/Target/R600/SILowerLiteralConstants.cpp<br>
llvm/trunk/lib/Target/R600/SIMachineFunctionInfo.cpp<br>
llvm/trunk/lib/Target/R600/SIMachineFunctionInfo.h<br>
llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp<br>
llvm/trunk/lib/Target/R600/SIRegisterInfo.h<br>
llvm/trunk/lib/Target/R600/SIRegisterInfo.td<br>
llvm/trunk/lib/Target/R600/SISchedule.td<br>
llvm/trunk/lib/Target/R600/TargetInfo/<br>
llvm/trunk/lib/Target/R600/TargetInfo/AMDGPUTargetInfo.cpp<br>
llvm/trunk/lib/Target/R600/TargetInfo/CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/TargetInfo/LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/TargetInfo/Makefile<br>
llvm/trunk/test/CodeGen/R600/add.v4i32.ll<br>
llvm/trunk/test/CodeGen/R600/and.v4i32.ll<br>
llvm/trunk/test/CodeGen/R600/fabs.ll<br>
llvm/trunk/test/CodeGen/R600/fadd.ll<br>
llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll<br>
llvm/trunk/test/CodeGen/R600/fcmp-cnd.ll<br>
llvm/trunk/test/CodeGen/R600/fcmp-cnde-int-args.ll<br>
llvm/trunk/test/CodeGen/R600/fcmp.ll<br>
llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll<br>
llvm/trunk/test/CodeGen/R600/floor.ll<br>
llvm/trunk/test/CodeGen/R600/fmax.ll<br>
llvm/trunk/test/CodeGen/R600/fmin.ll<br>
llvm/trunk/test/CodeGen/R600/fmul.ll<br>
llvm/trunk/test/CodeGen/R600/fmul.v4f32.ll<br>
llvm/trunk/test/CodeGen/R600/fsub.ll<br>
llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll<br>
llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll<br>
llvm/trunk/test/CodeGen/R600/icmp-select-sete-reverse-args.ll<br>
llvm/trunk/test/CodeGen/R600/lit.local.cfg<br>
llvm/trunk/test/CodeGen/R600/literals.ll<br>
llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll<br>
llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trunc.ll<br>
llvm/trunk/test/CodeGen/R600/llvm.cos.ll<br>
llvm/trunk/test/CodeGen/R600/llvm.pow.ll<br>
llvm/trunk/test/CodeGen/R600/llvm.sin.ll<br>
llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll<br>
llvm/trunk/test/CodeGen/R600/load.i8.ll<br>
llvm/trunk/test/CodeGen/R600/reciprocal.ll<br>
llvm/trunk/test/CodeGen/R600/sdiv.ll<br>
llvm/trunk/test/CodeGen/R600/selectcc-icmp-select-float.ll<br>
llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll<br>
llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll<br>
llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll<br>
llvm/trunk/test/CodeGen/R600/short-args.ll<br>
llvm/trunk/test/CodeGen/R600/store.v4f32.ll<br>
llvm/trunk/test/CodeGen/R600/store.v4i32.ll<br>
llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll<br>
llvm/trunk/test/CodeGen/R600/urem.v4i32.ll<br>
llvm/trunk/test/CodeGen/SI/<br>
llvm/trunk/test/CodeGen/SI/sanity.ll<br>
Modified:<br>
llvm/trunk/include/llvm/Intrinsics.td<br>
llvm/trunk/lib/Target/LLVMBuild.txt<br>
<br>
Modified: llvm/trunk/include/llvm/Intrinsics.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=169915&r1=169914&r2=169915&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=169915&r1=169914&r2=169915&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Intrinsics.td (original)<br>
+++ llvm/trunk/include/llvm/Intrinsics.td Tue Dec 11 15:25:42 2012<br>
@@ -472,3 +472,4 @@<br>
include "llvm/IntrinsicsHexagon.td"<br>
include "llvm/IntrinsicsNVVM.td"<br>
include "llvm/IntrinsicsMips.td"<br>
+include "llvm/IntrinsicsR600.td"<br>
<br>
Added: llvm/trunk/include/llvm/IntrinsicsR600.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsR600.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsR600.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IntrinsicsR600.td (added)<br>
+++ llvm/trunk/include/llvm/IntrinsicsR600.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,36 @@<br>
+//===- IntrinsicsR600.td - Defines R600 intrinsics ---------*- tablegen -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file defines all of the R600-specific intrinsics.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+let TargetPrefix = "r600" in {<br>
+<br>
+class R600ReadPreloadRegisterIntrinsic<string name><br>
+ : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<name>;<br>
+<br>
+multiclass R600ReadPreloadRegisterIntrinsic_xyz<string prefix> {<br>
+ def _x : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_x")>;<br>
+ def _y : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_y")>;<br>
+ def _z : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_z")>;<br>
+}<br>
+<br>
+defm int_r600_read_global_size : R600ReadPreloadRegisterIntrinsic_xyz <<br>
+ "__builtin_r600_read_global_size">;<br>
+defm int_r600_read_local_size : R600ReadPreloadRegisterIntrinsic_xyz <<br>
+ "__builtin_r600_read_local_size">;<br>
+defm int_r600_read_ngroups : R600ReadPreloadRegisterIntrinsic_xyz <<br>
+ "__builtin_r600_read_ngroups">;<br>
+defm int_r600_read_tgid : R600ReadPreloadRegisterIntrinsic_xyz <<br>
+ "__builtin_r600_read_tgid">;<br>
+defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <<br>
+ "__builtin_r600_read_tidig">;<br>
+} // End TargetPrefix = "r600"<br>
<br>
Modified: llvm/trunk/lib/Target/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=169915&r1=169914&r2=169915&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=169915&r1=169914&r2=169915&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/LLVMBuild.txt Tue Dec 11 15:25:42 2012<br>
@@ -16,7 +16,7 @@<br>
;===------------------------------------------------------------------------===;<br>
<br>
[common]<br>
-subdirectories = ARM CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore<br>
+subdirectories = ARM CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC R600 Sparc X86 XCore<br>
<br>
; This is a special group whose required libraries are extended (by llvm-build)<br>
; with the best execution engine (the native JIT, if available, or the<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPU.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPU.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPU.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,48 @@<br>
+//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+/// \file<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPU_H<br>
+#define AMDGPU_H<br>
+<br>
+#include "AMDGPUTargetMachine.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+class FunctionPass;<br>
+class AMDGPUTargetMachine;<br>
+<br>
+// R600 Passes<br>
+FunctionPass* createR600KernelParametersPass(const DataLayout *TD);<br>
+FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);<br>
+<br>
+// SI Passes<br>
+FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);<br>
+FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);<br>
+FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);<br>
+FunctionPass *createSILowerLiteralConstantsPass(TargetMachine &tm);<br>
+FunctionPass *createSIFixSGPRLivenessPass(TargetMachine &tm);<br>
+<br>
+// Passes common to R600 and SI<br>
+FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);<br>
+<br>
+} // End namespace llvm<br>
+<br>
+namespace ShaderType {<br>
+ enum Type {<br>
+ PIXEL = 0,<br>
+ VERTEX = 1,<br>
+ GEOMETRY = 2,<br>
+ COMPUTE = 3<br>
+ };<br>
+}<br>
+<br>
+#endif // AMDGPU_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPU.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPU.td (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPU.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,40 @@<br>
+//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//==-----------------------------------------------------------------------===//<br>
+<br>
+// Include AMDIL TD files<br>
+include "AMDILBase.td"<br>
+<br>
+<br>
+def AMDGPUInstrInfo : InstrInfo {<br>
+ let guessInstructionProperties = 1;<br>
+}<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Declare the target which we are implementing<br>
+//===----------------------------------------------------------------------===//<br>
+def AMDGPUAsmWriter : AsmWriter {<br>
+ string AsmWriterClassName = "InstPrinter";<br>
+ int Variant = 0;<br>
+ bit isMCAsmWriter = 1;<br>
+}<br>
+<br>
+def AMDGPU : Target {<br>
+ // Pull in Instruction Info:<br>
+ let InstructionSet = AMDGPUInstrInfo;<br>
+ let AssemblyWriters = [AMDGPUAsmWriter];<br>
+}<br>
+<br>
+// Include AMDGPU TD files<br>
+include "R600Schedule.td"<br>
+include "SISchedule.td"<br>
+include "Processors.td"<br>
+include "AMDGPUInstrInfo.td"<br>
+include "AMDGPUIntrinsics.td"<br>
+include "AMDGPURegisterInfo.td"<br>
+include "AMDGPUInstructions.td"<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,138 @@<br>
+//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+///<br>
+/// The AMDGPUAsmPrinter is used to print both assembly string and also binary<br>
+/// code. When passed an MCAsmStreamer it prints assembly and when passed<br>
+/// an MCObjectStreamer it outputs binary code.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+<br>
+<br>
+#include "AMDGPUAsmPrinter.h"<br>
+#include "AMDGPU.h"<br>
+#include "SIMachineFunctionInfo.h"<br>
+#include "SIRegisterInfo.h"<br>
+#include "llvm/MC/MCStreamer.h"<br>
+#include "llvm/Target/TargetLoweringObjectFile.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+<br>
+static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,<br>
+ MCStreamer &Streamer) {<br>
+ return new AMDGPUAsmPrinter(tm, Streamer);<br>
+}<br>
+<br>
+extern "C" void LLVMInitializeR600AsmPrinter() {<br>
+ TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);<br>
+}<br>
+<br>
+/// We need to override this function so we can avoid<br>
+/// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.<br>
+bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {<br>
+ const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();<br>
+ if (STM.dumpCode()) {<br>
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)<br>
+ MF.dump();<br>
+#endif<br>
+ }<br>
+ SetupMachineFunction(MF);<br>
+ OutStreamer.SwitchSection(getObjFileLowering().getTextSection());<br>
+ if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {<br>
+ EmitProgramInfo(MF);<br>
+ }<br>
+ EmitFunctionBody();<br>
+ return false;<br>
+}<br>
+<br>
+void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {<br>
+ unsigned MaxSGPR = 0;<br>
+ unsigned MaxVGPR = 0;<br>
+ bool VCCUsed = false;<br>
+ const SIRegisterInfo * RI =<br>
+ static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());<br>
+<br>
+ for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();<br>
+ BB != BB_E; ++BB) {<br>
+ MachineBasicBlock &MBB = *BB;<br>
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();<br>
+ I != E; ++I) {<br>
+ MachineInstr &MI = *I;<br>
+<br>
+ unsigned numOperands = MI.getNumOperands();<br>
+ for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {<br>
+ MachineOperand & MO = MI.getOperand(op_idx);<br>
+ unsigned maxUsed;<br>
+ unsigned width = 0;<br>
+ bool isSGPR = false;<br>
+ unsigned reg;<br>
+ unsigned hwReg;<br>
+ if (!MO.isReg()) {<br>
+ continue;<br>
+ }<br>
+ reg = MO.getReg();<br>
+ if (reg == AMDGPU::VCC) {<br>
+ VCCUsed = true;<br>
+ continue;<br>
+ }<br>
+ switch (reg) {<br>
+ default: break;<br>
+ case AMDGPU::EXEC:<br>
+ case AMDGPU::SI_LITERAL_CONSTANT:<br>
+ case AMDGPU::SREG_LIT_0:<br>
+ case AMDGPU::M0:<br>
+ continue;<br>
+ }<br>
+<br>
+ if (AMDGPU::SReg_32RegClass.contains(reg)) {<br>
+ isSGPR = true;<br>
+ width = 1;<br>
+ } else if (AMDGPU::VReg_32RegClass.contains(reg)) {<br>
+ isSGPR = false;<br>
+ width = 1;<br>
+ } else if (AMDGPU::SReg_64RegClass.contains(reg)) {<br>
+ isSGPR = true;<br>
+ width = 2;<br>
+ } else if (AMDGPU::VReg_64RegClass.contains(reg)) {<br>
+ isSGPR = false;<br>
+ width = 2;<br>
+ } else if (AMDGPU::SReg_128RegClass.contains(reg)) {<br>
+ isSGPR = true;<br>
+ width = 4;<br>
+ } else if (AMDGPU::VReg_128RegClass.contains(reg)) {<br>
+ isSGPR = false;<br>
+ width = 4;<br>
+ } else if (AMDGPU::SReg_256RegClass.contains(reg)) {<br>
+ isSGPR = true;<br>
+ width = 8;<br>
+ } else {<br>
+ assert(!"Unknown register class");<br>
+ }<br>
+ hwReg = RI->getEncodingValue(reg);<br>
+ maxUsed = hwReg + width - 1;<br>
+ if (isSGPR) {<br>
+ MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;<br>
+ } else {<br>
+ MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+ if (VCCUsed) {<br>
+ MaxSGPR += 2;<br>
+ }<br>
+ SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();<br>
+ OutStreamer.EmitIntValue(MaxSGPR + 1, 4);<br>
+ OutStreamer.EmitIntValue(MaxVGPR + 1, 4);<br>
+ OutStreamer.EmitIntValue(MFI->SPIPSInputAddr, 4);<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,44 @@<br>
+//===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code -------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief AMDGPU Assembly printer class.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPU_ASMPRINTER_H<br>
+#define AMDGPU_ASMPRINTER_H<br>
+<br>
+#include "llvm/CodeGen/AsmPrinter.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+class AMDGPUAsmPrinter : public AsmPrinter {<br>
+<br>
+public:<br>
+ explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)<br>
+ : AsmPrinter(TM, Streamer) { }<br>
+<br>
+ virtual bool runOnMachineFunction(MachineFunction &MF);<br>
+<br>
+ virtual const char *getPassName() const {<br>
+ return "AMDGPU Assembly Printer";<br>
+ }<br>
+<br>
+ /// \brief Emit register usage information so that the GPU driver<br>
+ /// can correctly setup the GPU state.<br>
+ void EmitProgramInfo(MachineFunction &MF);<br>
+<br>
+ /// Implemented in AMDGPUMCInstLower.cpp<br>
+ virtual void EmitInstruction(const MachineInstr *MI);<br>
+};<br>
+<br>
+} // End anonymous llvm<br>
+<br>
+#endif //AMDGPU_ASMPRINTER_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUCodeEmitter.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,49 @@<br>
+//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief CodeEmitter interface for R600 and SI codegen.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPUCODEEMITTER_H<br>
+#define AMDGPUCODEEMITTER_H<br>
+<br>
+namespace llvm {<br>
+<br>
+class AMDGPUCodeEmitter {<br>
+public:<br>
+ uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;<br>
+ virtual uint64_t getMachineOpValue(const MachineInstr &MI,<br>
+ const MachineOperand &MO) const { return 0; }<br>
+ virtual unsigned GPR4AlignEncode(const MachineInstr &MI,<br>
+ unsigned OpNo) const {<br>
+ return 0;<br>
+ }<br>
+ virtual unsigned GPR2AlignEncode(const MachineInstr &MI,<br>
+ unsigned OpNo) const {<br>
+ return 0;<br>
+ }<br>
+ virtual uint64_t VOPPostEncode(const MachineInstr &MI,<br>
+ uint64_t Value) const {<br>
+ return Value;<br>
+ }<br>
+ virtual uint64_t i32LiteralEncode(const MachineInstr &MI,<br>
+ unsigned OpNo) const {<br>
+ return 0;<br>
+ }<br>
+ virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)<br>
+ const {<br>
+ return 0;<br>
+ }<br>
+};<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif // AMDGPUCODEEMITTER_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUConvertToISA.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,62 @@<br>
+//===-- AMDGPUConvertToISA.cpp - Lower AMDIL to HW ISA --------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief This pass lowers AMDIL machine instructions to the appropriate<br>
+/// hardware instructions.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPU.h"<br>
+#include "AMDGPUInstrInfo.h"<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+namespace {<br>
+<br>
+class AMDGPUConvertToISAPass : public MachineFunctionPass {<br>
+<br>
+private:<br>
+ static char ID;<br>
+ TargetMachine &TM;<br>
+<br>
+public:<br>
+ AMDGPUConvertToISAPass(TargetMachine &tm) :<br>
+ MachineFunctionPass(ID), TM(tm) { }<br>
+<br>
+ virtual bool runOnMachineFunction(MachineFunction &MF);<br>
+<br>
+ virtual const char *getPassName() const {return "AMDGPU Convert to ISA";}<br>
+<br>
+};<br>
+<br>
+} // End anonymous namespace<br>
+<br>
+char AMDGPUConvertToISAPass::ID = 0;<br>
+<br>
+FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &tm) {<br>
+ return new AMDGPUConvertToISAPass(tm);<br>
+}<br>
+<br>
+bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF) {<br>
+ const AMDGPUInstrInfo * TII =<br>
+ static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo());<br>
+<br>
+ for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();<br>
+ BB != BB_E; ++BB) {<br>
+ MachineBasicBlock &MBB = *BB;<br>
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();<br>
+ I != E; ++I) {<br>
+ MachineInstr &MI = *I;<br>
+ TII->convertToISA(MI, MF, MBB.findDebugLoc(I));<br>
+ }<br>
+ }<br>
+ return false;<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,417 @@<br>
+//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief This is the parent TargetLowering class for hardware code gen<br>
+/// targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPUISelLowering.h"<br>
+#include "AMDILIntrinsicInfo.h"<br>
+#include "llvm/CodeGen/MachineFunction.h"<br>
+#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
+#include "llvm/CodeGen/SelectionDAG.h"<br>
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :<br>
+ TargetLowering(TM, new TargetLoweringObjectFileELF()) {<br>
+<br>
+ // Initialize target lowering borrowed from AMDIL<br>
+ InitAMDILLowering();<br>
+<br>
+ // We need to custom lower some of the intrinsics<br>
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);<br>
+<br>
+ // Library functions. These default to Expand, but we have instructions<br>
+ // for them.<br>
+ setOperationAction(ISD::FCEIL, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FEXP2, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FPOW, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FLOG2, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FABS, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FFLOOR, MVT::f32, Legal);<br>
+ setOperationAction(ISD::FRINT, MVT::f32, Legal);<br>
+<br>
+ // Lower floating point store/load to integer store/load to reduce the number<br>
+ // of patterns in tablegen.<br>
+ setOperationAction(ISD::STORE, MVT::f32, Promote);<br>
+ AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);<br>
+<br>
+ setOperationAction(ISD::STORE, MVT::v4f32, Promote);<br>
+ AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);<br>
+<br>
+ setOperationAction(ISD::LOAD, MVT::f32, Promote);<br>
+ AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);<br>
+<br>
+ setOperationAction(ISD::LOAD, MVT::v4f32, Promote);<br>
+ AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);<br>
+<br>
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);<br>
+ setOperationAction(ISD::UDIVREM, MVT::i32, Custom);<br>
+ setOperationAction(ISD::UREM, MVT::i32, Expand);<br>
+}<br>
+<br>
+//===---------------------------------------------------------------------===//<br>
+// TargetLowering Callbacks<br>
+//===---------------------------------------------------------------------===//<br>
+<br>
+SDValue AMDGPUTargetLowering::LowerFormalArguments(<br>
+ SDValue Chain,<br>
+ CallingConv::ID CallConv,<br>
+ bool isVarArg,<br>
+ const SmallVectorImpl<ISD::InputArg> &Ins,<br>
+ DebugLoc DL, SelectionDAG &DAG,<br>
+ SmallVectorImpl<SDValue> &InVals) const {<br>
+ for (unsigned i = 0, e = Ins.size(); i < e; ++i) {<br>
+ InVals.push_back(SDValue());<br>
+ }<br>
+ return Chain;<br>
+}<br>
+<br>
+SDValue AMDGPUTargetLowering::LowerReturn(<br>
+ SDValue Chain,<br>
+ CallingConv::ID CallConv,<br>
+ bool isVarArg,<br>
+ const SmallVectorImpl<ISD::OutputArg> &Outs,<br>
+ const SmallVectorImpl<SDValue> &OutVals,<br>
+ DebugLoc DL, SelectionDAG &DAG) const {<br>
+ return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);<br>
+}<br>
+<br>
+//===---------------------------------------------------------------------===//<br>
+// Target specific lowering<br>
+//===---------------------------------------------------------------------===//<br>
+<br>
+SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)<br>
+ const {<br>
+ switch (Op.getOpcode()) {<br>
+ default:<br>
+ Op.getNode()->dump();<br>
+ assert(0 && "Custom lowering code for this"<br>
+ "instruction is not implemented yet!");<br>
+ break;<br>
+ // AMDIL DAG lowering<br>
+ case ISD::SDIV: return LowerSDIV(Op, DAG);<br>
+ case ISD::SREM: return LowerSREM(Op, DAG);<br>
+ case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);<br>
+ case ISD::BRCOND: return LowerBRCOND(Op, DAG);<br>
+ // AMDGPU DAG lowering<br>
+ case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);<br>
+ case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);<br>
+ }<br>
+ return Op;<br>
+}<br>
+<br>
+SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();<br>
+ DebugLoc DL = Op.getDebugLoc();<br>
+ EVT VT = Op.getValueType();<br>
+<br>
+ switch (IntrinsicID) {<br>
+ default: return Op;<br>
+ case AMDGPUIntrinsic::AMDIL_abs:<br>
+ return LowerIntrinsicIABS(Op, DAG);<br>
+ case AMDGPUIntrinsic::AMDIL_exp:<br>
+ return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));<br>
+ case AMDGPUIntrinsic::AMDGPU_lrp:<br>
+ return LowerIntrinsicLRP(Op, DAG);<br>
+ case AMDGPUIntrinsic::AMDIL_fraction:<br>
+ return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));<br>
+ case AMDGPUIntrinsic::AMDIL_mad:<br>
+ return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2), Op.getOperand(3));<br>
+ case AMDGPUIntrinsic::AMDIL_max:<br>
+ return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDGPU_imax:<br>
+ return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDGPU_umax:<br>
+ return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDIL_min:<br>
+ return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDGPU_imin:<br>
+ return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDGPU_umin:<br>
+ return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2));<br>
+ case AMDGPUIntrinsic::AMDIL_round_nearest:<br>
+ return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));<br>
+ }<br>
+}<br>
+<br>
+///IABS(a) = SMAX(sub(0, a), a)<br>
+SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+<br>
+ DebugLoc DL = Op.getDebugLoc();<br>
+ EVT VT = Op.getValueType();<br>
+ SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),<br>
+ Op.getOperand(1));<br>
+<br>
+ return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));<br>
+}<br>
+<br>
+/// Linear Interpolation<br>
+/// LRP(a, b, c) = muladd(a, b, (1 - a) * c)<br>
+SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ DebugLoc DL = Op.getDebugLoc();<br>
+ EVT VT = Op.getValueType();<br>
+ SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,<br>
+ DAG.getConstantFP(1.0f, MVT::f32),<br>
+ Op.getOperand(1));<br>
+ SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,<br>
+ Op.getOperand(3));<br>
+ return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),<br>
+ Op.getOperand(2),<br>
+ OneSubAC);<br>
+}<br>
+<br>
+/// \brief Generate Min/Max node<br>
+SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ DebugLoc DL = Op.getDebugLoc();<br>
+ EVT VT = Op.getValueType();<br>
+<br>
+ SDValue LHS = Op.getOperand(0);<br>
+ SDValue RHS = Op.getOperand(1);<br>
+ SDValue True = Op.getOperand(2);<br>
+ SDValue False = Op.getOperand(3);<br>
+ SDValue CC = Op.getOperand(4);<br>
+<br>
+ if (VT != MVT::f32 ||<br>
+ !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {<br>
+ return SDValue();<br>
+ }<br>
+<br>
+ ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();<br>
+ switch (CCOpcode) {<br>
+ case ISD::SETOEQ:<br>
+ case ISD::SETONE:<br>
+ case ISD::SETUNE:<br>
+ case ISD::SETNE:<br>
+ case ISD::SETUEQ:<br>
+ case ISD::SETEQ:<br>
+ case ISD::SETFALSE:<br>
+ case ISD::SETFALSE2:<br>
+ case ISD::SETTRUE:<br>
+ case ISD::SETTRUE2:<br>
+ case ISD::SETUO:<br>
+ case ISD::SETO:<br>
+ assert(0 && "Operation should already be optimised !");<br>
+ case ISD::SETULE:<br>
+ case ISD::SETULT:<br>
+ case ISD::SETOLE:<br>
+ case ISD::SETOLT:<br>
+ case ISD::SETLE:<br>
+ case ISD::SETLT: {<br>
+ if (LHS == True)<br>
+ return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);<br>
+ else<br>
+ return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);<br>
+ }<br>
+ case ISD::SETGT:<br>
+ case ISD::SETGE:<br>
+ case ISD::SETUGE:<br>
+ case ISD::SETOGE:<br>
+ case ISD::SETUGT:<br>
+ case ISD::SETOGT: {<br>
+ if (LHS == True)<br>
+ return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);<br>
+ else<br>
+ return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);<br>
+ }<br>
+ case ISD::SETCC_INVALID:<br>
+ assert(0 && "Invalid setcc condcode !");<br>
+ }<br>
+ return Op;<br>
+}<br>
+<br>
+<br>
+<br>
+SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ DebugLoc DL = Op.getDebugLoc();<br>
+ EVT VT = Op.getValueType();<br>
+<br>
+ SDValue Num = Op.getOperand(0);<br>
+ SDValue Den = Op.getOperand(1);<br>
+<br>
+ SmallVector<SDValue, 8> Results;<br>
+<br>
+ // RCP = URECIP(Den) = 2^32 / Den + e<br>
+ // e is rounding error.<br>
+ SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);<br>
+<br>
+ // RCP_LO = umulo(RCP, Den) */<br>
+ SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);<br>
+<br>
+ // RCP_HI = mulhu (RCP, Den) */<br>
+ SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);<br>
+<br>
+ // NEG_RCP_LO = -RCP_LO<br>
+ SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),<br>
+ RCP_LO);<br>
+<br>
+ // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)<br>
+ SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),<br>
+ NEG_RCP_LO, RCP_LO,<br>
+ ISD::SETEQ);<br>
+ // Calculate the rounding error from the URECIP instruction<br>
+ // E = mulhu(ABS_RCP_LO, RCP)<br>
+ SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);<br>
+<br>
+ // RCP_A_E = RCP + E<br>
+ SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);<br>
+<br>
+ // RCP_S_E = RCP - E<br>
+ SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);<br>
+<br>
+ // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)<br>
+ SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),<br>
+ RCP_A_E, RCP_S_E,<br>
+ ISD::SETEQ);<br>
+ // Quotient = mulhu(Tmp0, Num)<br>
+ SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);<br>
+<br>
+ // Num_S_Remainder = Quotient * Den<br>
+ SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);<br>
+<br>
+ // Remainder = Num - Num_S_Remainder<br>
+ SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);<br>
+<br>
+ // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)<br>
+ SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,<br>
+ DAG.getConstant(-1, VT),<br>
+ DAG.getConstant(0, VT),<br>
+ ISD::SETGE);<br>
+ // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)<br>
+ SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,<br>
+ DAG.getConstant(0, VT),<br>
+ DAG.getConstant(-1, VT),<br>
+ DAG.getConstant(0, VT),<br>
+ ISD::SETGE);<br>
+ // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero<br>
+ SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,<br>
+ Remainder_GE_Zero);<br>
+<br>
+ // Calculate Division result:<br>
+<br>
+ // Quotient_A_One = Quotient + 1<br>
+ SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,<br>
+ DAG.getConstant(1, VT));<br>
+<br>
+ // Quotient_S_One = Quotient - 1<br>
+ SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,<br>
+ DAG.getConstant(1, VT));<br>
+<br>
+ // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)<br>
+ SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),<br>
+ Quotient, Quotient_A_One, ISD::SETEQ);<br>
+<br>
+ // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)<br>
+ Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),<br>
+ Quotient_S_One, Div, ISD::SETEQ);<br>
+<br>
+ // Calculate Rem result:<br>
+<br>
+ // Remainder_S_Den = Remainder - Den<br>
+ SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);<br>
+<br>
+ // Remainder_A_Den = Remainder + Den<br>
+ SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);<br>
+<br>
+ // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)<br>
+ SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),<br>
+ Remainder, Remainder_S_Den, ISD::SETEQ);<br>
+<br>
+ // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)<br>
+ Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),<br>
+ Remainder_A_Den, Rem, ISD::SETEQ);<br>
+ SDValue Ops[2];<br>
+ Ops[0] = Div;<br>
+ Ops[1] = Rem;<br>
+ return DAG.getMergeValues(Ops, 2, DL);<br>
+}<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Helper functions<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {<br>
+ if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {<br>
+ return CFP->isExactlyValue(1.0);<br>
+ }<br>
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
+ return C->isAllOnesValue();<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {<br>
+ if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {<br>
+ return CFP->getValueAPF().isZero();<br>
+ }<br>
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
+ return C->isNullValue();<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,<br>
+ const TargetRegisterClass *RC,<br>
+ unsigned Reg, EVT VT) const {<br>
+ MachineFunction &MF = DAG.getMachineFunction();<br>
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+ unsigned VirtualRegister;<br>
+ if (!MRI.isLiveIn(Reg)) {<br>
+ VirtualRegister = MRI.createVirtualRegister(RC);<br>
+ MRI.addLiveIn(Reg, VirtualRegister);<br>
+ } else {<br>
+ VirtualRegister = MRI.getLiveInVirtReg(Reg);<br>
+ }<br>
+ return DAG.getRegister(VirtualRegister, VT);<br>
+}<br>
+<br>
+#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;<br>
+<br>
+const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {<br>
+ switch (Opcode) {<br>
+ default: return 0;<br>
+ // AMDIL DAG nodes<br>
+ NODE_NAME_CASE(MAD);<br>
+ NODE_NAME_CASE(CALL);<br>
+ NODE_NAME_CASE(UMUL);<br>
+ NODE_NAME_CASE(DIV_INF);<br>
+ NODE_NAME_CASE(RET_FLAG);<br>
+ NODE_NAME_CASE(BRANCH_COND);<br>
+<br>
+ // AMDGPU DAG nodes<br>
+ NODE_NAME_CASE(DWORDADDR)<br>
+ NODE_NAME_CASE(FRACT)<br>
+ NODE_NAME_CASE(FMAX)<br>
+ NODE_NAME_CASE(SMAX)<br>
+ NODE_NAME_CASE(UMAX)<br>
+ NODE_NAME_CASE(FMIN)<br>
+ NODE_NAME_CASE(SMIN)<br>
+ NODE_NAME_CASE(UMIN)<br>
+ NODE_NAME_CASE(URECIP)<br>
+ NODE_NAME_CASE(INTERP)<br>
+ NODE_NAME_CASE(INTERP_P0)<br>
+ NODE_NAME_CASE(EXPORT)<br>
+ }<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,144 @@<br>
+//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Interface definition of the TargetLowering class that is common<br>
+/// to all AMD GPUs.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPUISELLOWERING_H<br>
+#define AMDGPUISELLOWERING_H<br>
+<br>
+#include "llvm/Target/TargetLowering.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+class MachineRegisterInfo;<br>
+<br>
+class AMDGPUTargetLowering : public TargetLowering {<br>
+private:<br>
+ SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;<br>
+<br>
+protected:<br>
+<br>
+ /// \brief Helper function that adds Reg to the LiveIn list of the DAG's<br>
+ /// MachineFunction.<br>
+ ///<br>
+ /// \returns a RegisterSDNode representing Reg.<br>
+ SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,<br>
+ unsigned Reg, EVT VT) const;<br>
+<br>
+ bool isHWTrueValue(SDValue Op) const;<br>
+ bool isHWFalseValue(SDValue Op) const;<br>
+<br>
+public:<br>
+ AMDGPUTargetLowering(TargetMachine &TM);<br>
+<br>
+ virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,<br>
+ bool isVarArg,<br>
+ const SmallVectorImpl<ISD::InputArg> &Ins,<br>
+ DebugLoc DL, SelectionDAG &DAG,<br>
+ SmallVectorImpl<SDValue> &InVals) const;<br>
+<br>
+ virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,<br>
+ bool isVarArg,<br>
+ const SmallVectorImpl<ISD::OutputArg> &Outs,<br>
+ const SmallVectorImpl<SDValue> &OutVals,<br>
+ DebugLoc DL, SelectionDAG &DAG) const;<br>
+<br>
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;<br>
+ virtual const char* getTargetNodeName(unsigned Opcode) const;<br>
+<br>
+// Functions defined in AMDILISelLowering.cpp<br>
+public:<br>
+<br>
+ /// \brief Determine which of the bits specified in \p Mask are known to be<br>
+ /// either zero or one and return them in the \p KnownZero and \p KnownOne<br>
+ /// bitsets.<br>
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,<br>
+ APInt &KnownZero,<br>
+ APInt &KnownOne,<br>
+ const SelectionDAG &DAG,<br>
+ unsigned Depth = 0) const;<br>
+<br>
+ virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,<br>
+ const CallInst &I, unsigned Intrinsic) const;<br>
+<br>
+ /// We want to mark f32/f64 floating point values as legal.<br>
+ bool isFPImmLegal(const APFloat &Imm, EVT VT) const;<br>
+<br>
+ /// We don't want to shrink f64/f32 constants.<br>
+ bool ShouldShrinkFPConstant(EVT VT) const;<br>
+<br>
+private:<br>
+ void InitAMDILLowering();<br>
+ SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;<br>
+ EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;<br>
+ SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;<br>
+};<br>
+<br>
+namespace AMDGPUISD {<br>
+<br>
+enum {<br>
+ // AMDIL ISD Opcodes<br>
+ FIRST_NUMBER = ISD::BUILTIN_OP_END,<br>
+ MAD, // 32bit Fused Multiply Add instruction<br>
+ CALL, // Function call based on a single integer<br>
+ UMUL, // 32bit unsigned multiplication<br>
+ DIV_INF, // Divide with infinity returned on zero divisor<br>
+ RET_FLAG,<br>
+ BRANCH_COND,<br>
+ // End AMDIL ISD Opcodes<br>
+ BITALIGN,<br>
+ DWORDADDR,<br>
+ FRACT,<br>
+ FMAX,<br>
+ SMAX,<br>
+ UMAX,<br>
+ FMIN,<br>
+ SMIN,<br>
+ UMIN,<br>
+ URECIP,<br>
+ INTERP,<br>
+ INTERP_P0,<br>
+ EXPORT,<br>
+ LAST_AMDGPU_ISD_NUMBER<br>
+};<br>
+<br>
+<br>
+} // End namespace AMDGPUISD<br>
+<br>
+namespace SIISD {<br>
+<br>
+enum {<br>
+ SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER,<br>
+ VCC_AND,<br>
+ VCC_BITCAST<br>
+};<br>
+<br>
+} // End namespace SIISD<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif // AMDGPUISELLOWERING_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,257 @@<br>
+//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Implementation of the TargetInstrInfo class that is common to all<br>
+/// AMD GPUs.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPUInstrInfo.h"<br>
+#include "AMDGPURegisterInfo.h"<br>
+#include "AMDGPUTargetMachine.h"<br>
+#include "AMDIL.h"<br>
+#include "llvm/CodeGen/MachineFrameInfo.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
+#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
+<br>
+#define GET_INSTRINFO_CTOR<br>
+#include "AMDGPUGenInstrInfo.inc"<br>
+<br>
+using namespace llvm;<br>
+<br>
+AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)<br>
+ : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }<br>
+<br>
+const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {<br>
+ return RI;<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,<br>
+ unsigned &SrcReg, unsigned &DstReg,<br>
+ unsigned &SubIdx) const {<br>
+// TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+<br>
+unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,<br>
+ const MachineMemOperand *&MMO,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return false;<br>
+}<br>
+unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,<br>
+ const MachineMemOperand *&MMO,<br>
+ int &FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+MachineInstr *<br>
+AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,<br>
+ MachineBasicBlock::iterator &MBBI,<br>
+ LiveVariables *LV) const {<br>
+// TODO: Implement this function<br>
+ return NULL;<br>
+}<br>
+bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,<br>
+ MachineBasicBlock &MBB) const {<br>
+ while (iter != MBB.end()) {<br>
+ switch (iter->getOpcode()) {<br>
+ default:<br>
+ break;<br>
+ case AMDGPU::BRANCH_COND_i32:<br>
+ case AMDGPU::BRANCH_COND_f32:<br>
+ case AMDGPU::BRANCH:<br>
+ return true;<br>
+ };<br>
+ ++iter;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+MachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) {<br>
+ MachineBasicBlock::iterator tmp = MBB->end();<br>
+ if (!MBB->size()) {<br>
+ return MBB->end();<br>
+ }<br>
+ while (--tmp) {<br>
+ if (tmp->getOpcode() == AMDGPU::ENDLOOP<br>
+ || tmp->getOpcode() == AMDGPU::ENDIF<br>
+ || tmp->getOpcode() == AMDGPU::ELSE) {<br>
+ if (tmp == MBB->begin()) {<br>
+ return tmp;<br>
+ } else {<br>
+ continue;<br>
+ }<br>
+ } else {<br>
+ return ++tmp;<br>
+ }<br>
+ }<br>
+ return MBB->end();<br>
+}<br>
+<br>
+void<br>
+AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI,<br>
+ unsigned SrcReg, bool isKill,<br>
+ int FrameIndex,<br>
+ const TargetRegisterClass *RC,<br>
+ const TargetRegisterInfo *TRI) const {<br>
+ assert(!"Not Implemented");<br>
+}<br>
+<br>
+void<br>
+AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI,<br>
+ unsigned DestReg, int FrameIndex,<br>
+ const TargetRegisterClass *RC,<br>
+ const TargetRegisterInfo *TRI) const {<br>
+ assert(!"Not Implemented");<br>
+}<br>
+<br>
+MachineInstr *<br>
+AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,<br>
+ MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops,<br>
+ int FrameIndex) const {<br>
+// TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+MachineInstr*<br>
+AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,<br>
+ MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops,<br>
+ MachineInstr *LoadMI) const {<br>
+ // TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+bool<br>
+AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops) const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+bool<br>
+AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,<br>
+ unsigned Reg, bool UnfoldLoad,<br>
+ bool UnfoldStore,<br>
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+bool<br>
+AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,<br>
+ SmallVectorImpl<SDNode*> &NewNodes) const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+unsigned<br>
+AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,<br>
+ bool UnfoldLoad, bool UnfoldStore,<br>
+ unsigned *LoadRegIndex) const {<br>
+ // TODO: Implement this function<br>
+ return 0;<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,<br>
+ int64_t Offset1, int64_t Offset2,<br>
+ unsigned NumLoads) const {<br>
+ assert(Offset2 > Offset1<br>
+ && "Second offset should be larger than first offset!");<br>
+ // If we have less than 16 loads in a row, and the offsets are within 16,<br>
+ // then schedule together.<br>
+ // TODO: Make the loads schedule near if it fits in a cacheline<br>
+ return (NumLoads < 16 && (Offset2 - Offset1) < 16);<br>
+}<br>
+<br>
+bool<br>
+AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)<br>
+ const {<br>
+ // TODO: Implement this function<br>
+ return true;<br>
+}<br>
+void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI) const {<br>
+ // TODO: Implement this function<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+bool<br>
+AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,<br>
+ const SmallVectorImpl<MachineOperand> &Pred2)<br>
+ const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,<br>
+ std::vector<MachineOperand> &Pred) const {<br>
+ // TODO: Implement this function<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {<br>
+ // TODO: Implement this function<br>
+ return MI->getDesc().isPredicable();<br>
+}<br>
+<br>
+bool<br>
+AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {<br>
+ // TODO: Implement this function<br>
+ return true;<br>
+}<br>
+<br>
+void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,<br>
+ DebugLoc DL) const {<br>
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+ const AMDGPURegisterInfo & RI = getRegisterInfo();<br>
+<br>
+ for (unsigned i = 0; i < MI.getNumOperands(); i++) {<br>
+ MachineOperand &MO = MI.getOperand(i);<br>
+ // Convert dst regclass to one that is supported by the ISA<br>
+ if (MO.isReg() && MO.isDef()) {<br>
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {<br>
+ const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());<br>
+ const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);<br>
+<br>
+ assert(newRegClass);<br>
+<br>
+ MRI.setRegClass(MO.getReg(), newRegClass);<br>
+ }<br>
+ }<br>
+ }<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,149 @@<br>
+//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Contains the definition of a TargetInstrInfo class that is common<br>
+/// to all AMD GPUs.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPUINSTRUCTIONINFO_H<br>
+#define AMDGPUINSTRUCTIONINFO_H<br>
+<br>
+#include "AMDGPURegisterInfo.h"<br>
+#include "AMDGPUInstrInfo.h"<br>
+#include "llvm/Target/TargetInstrInfo.h"<br>
+<br>
+#include <map><br>
+<br>
+#define GET_INSTRINFO_HEADER<br>
+#define GET_INSTRINFO_ENUM<br>
+#include "AMDGPUGenInstrInfo.inc"<br>
+<br>
+#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT<br>
+#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT<br>
+#define OPCODE_IS_ZERO AMDGPU::PRED_SETE<br>
+#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE<br>
+<br>
+namespace llvm {<br>
+<br>
+class AMDGPUTargetMachine;<br>
+class MachineFunction;<br>
+class MachineInstr;<br>
+class MachineInstrBuilder;<br>
+<br>
+class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {<br>
+private:<br>
+ const AMDGPURegisterInfo RI;<br>
+ TargetMachine &TM;<br>
+ bool getNextBranchInstr(MachineBasicBlock::iterator &iter,<br>
+ MachineBasicBlock &MBB) const;<br>
+public:<br>
+ explicit AMDGPUInstrInfo(TargetMachine &tm);<br>
+<br>
+ virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;<br>
+<br>
+ bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,<br>
+ unsigned &DstReg, unsigned &SubIdx) const;<br>
+<br>
+ unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;<br>
+ unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,<br>
+ int &FrameIndex) const;<br>
+ bool hasLoadFromStackSlot(const MachineInstr *MI,<br>
+ const MachineMemOperand *&MMO,<br>
+ int &FrameIndex) const;<br>
+ unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;<br>
+ unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,<br>
+ int &FrameIndex) const;<br>
+ bool hasStoreFromStackSlot(const MachineInstr *MI,<br>
+ const MachineMemOperand *&MMO,<br>
+ int &FrameIndex) const;<br>
+<br>
+ MachineInstr *<br>
+ convertToThreeAddress(MachineFunction::iterator &MFI,<br>
+ MachineBasicBlock::iterator &MBBI,<br>
+ LiveVariables *LV) const;<br>
+<br>
+<br>
+ virtual void copyPhysReg(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI, DebugLoc DL,<br>
+ unsigned DestReg, unsigned SrcReg,<br>
+ bool KillSrc) const = 0;<br>
+<br>
+ void storeRegToStackSlot(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI,<br>
+ unsigned SrcReg, bool isKill, int FrameIndex,<br>
+ const TargetRegisterClass *RC,<br>
+ const TargetRegisterInfo *TRI) const;<br>
+ void loadRegFromStackSlot(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI,<br>
+ unsigned DestReg, int FrameIndex,<br>
+ const TargetRegisterClass *RC,<br>
+ const TargetRegisterInfo *TRI) const;<br>
+<br>
+protected:<br>
+ MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,<br>
+ MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops,<br>
+ int FrameIndex) const;<br>
+ MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,<br>
+ MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops,<br>
+ MachineInstr *LoadMI) const;<br>
+public:<br>
+ bool canFoldMemoryOperand(const MachineInstr *MI,<br>
+ const SmallVectorImpl<unsigned> &Ops) const;<br>
+ bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,<br>
+ unsigned Reg, bool UnfoldLoad, bool UnfoldStore,<br>
+ SmallVectorImpl<MachineInstr *> &NewMIs) const;<br>
+ bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,<br>
+ SmallVectorImpl<SDNode *> &NewNodes) const;<br>
+ unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,<br>
+ bool UnfoldLoad, bool UnfoldStore,<br>
+ unsigned *LoadRegIndex = 0) const;<br>
+ bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,<br>
+ int64_t Offset1, int64_t Offset2,<br>
+ unsigned NumLoads) const;<br>
+<br>
+ bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;<br>
+ void insertNoop(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MI) const;<br>
+ bool isPredicated(const MachineInstr *MI) const;<br>
+ bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,<br>
+ const SmallVectorImpl<MachineOperand> &Pred2) const;<br>
+ bool DefinesPredicate(MachineInstr *MI,<br>
+ std::vector<MachineOperand> &Pred) const;<br>
+ bool isPredicable(MachineInstr *MI) const;<br>
+ bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;<br>
+<br>
+ // Helper functions that check the opcode for status information<br>
+ bool isLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isExtLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isSExtLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isZExtLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isAExtLoadInst(llvm::MachineInstr *MI) const;<br>
+ bool isStoreInst(llvm::MachineInstr *MI) const;<br>
+ bool isTruncStoreInst(llvm::MachineInstr *MI) const;<br>
+<br>
+ virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,<br>
+ int64_t Imm) const = 0;<br>
+ virtual unsigned getIEQOpcode() const = 0;<br>
+ virtual bool isMov(unsigned opcode) const = 0;<br>
+<br>
+ /// \brief Convert the AMDIL MachineInstr to a supported ISA<br>
+ /// MachineInstr<br>
+ virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,<br>
+ DebugLoc DL) const;<br>
+<br>
+};<br>
+<br>
+} // End llvm namespace<br>
+<br>
+#endif // AMDGPUINSTRINFO_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,74 @@<br>
+//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains DAG node defintions for the AMDGPU target.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// AMDGPU DAG Profiles<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [<br>
+ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3><br>
+]>;<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// AMDGPU DAG Nodes<br>
+//<br>
+<br>
+// out = ((a << 32) | b) >> c)<br>
+//<br>
+// Can be used to optimize rtol:<br>
+// rotl(a, b) = bitalign(a, a, 32 - b)<br>
+def AMDGPUbitalign : SDNode<"AMDGPUISD::BITALIGN", AMDGPUDTIntTernaryOp>;<br>
+<br>
+// This argument to this node is a dword address.<br>
+def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;<br>
+<br>
+// out = a - floor(a)<br>
+def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;<br>
+<br>
+// out = max(a, b) a and b are floats<br>
+def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// out = max(a, b) a and b are signed ints<br>
+def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// out = max(a, b) a and b are unsigned ints<br>
+def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// out = min(a, b) a and b are floats<br>
+def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// out = min(a, b) a snd b are signed ints<br>
+def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// out = min(a, b) a and b are unsigned ints<br>
+def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,<br>
+ [SDNPCommutative, SDNPAssociative]<br>
+>;<br>
+<br>
+// urecip - This operation is a helper for integer division, it returns the<br>
+// result of 1 / a as a fractional unsigned integer.<br>
+// out = (2^32 / a) + e<br>
+// e is rounding error<br>
+def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;<br>
+<br>
+def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstructions.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstructions.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUInstructions.td (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUInstructions.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,190 @@<br>
+//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains instruction defs that are common to all hw codegen<br>
+// targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {<br>
+ field bits<16> AMDILOp = 0;<br>
+ field bits<3> Gen = 0;<br>
+<br>
+ let Namespace = "AMDGPU";<br>
+ let OutOperandList = outs;<br>
+ let InOperandList = ins;<br>
+ let AsmString = asm;<br>
+ let Pattern = pattern;<br>
+ let Itinerary = NullALU;<br>
+ let TSFlags{42-40} = Gen;<br>
+ let TSFlags{63-48} = AMDILOp;<br>
+}<br>
+<br>
+class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern><br>
+ : AMDGPUInst<outs, ins, asm, pattern> {<br>
+<br>
+ field bits<32> Inst = 0xffffffff;<br>
+<br>
+}<br>
+<br>
+def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;<br>
+<br>
+def COND_EQ : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETOEQ: case ISD::SETUEQ:<br>
+ case ISD::SETEQ: return true;}}}]<br>
+>;<br>
+<br>
+def COND_NE : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETONE: case ISD::SETUNE:<br>
+ case ISD::SETNE: return true;}}}]<br>
+>;<br>
+def COND_GT : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETOGT: case ISD::SETUGT:<br>
+ case ISD::SETGT: return true;}}}]<br>
+>;<br>
+<br>
+def COND_GE : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETOGE: case ISD::SETUGE:<br>
+ case ISD::SETGE: return true;}}}]<br>
+>;<br>
+<br>
+def COND_LT : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETOLT: case ISD::SETULT:<br>
+ case ISD::SETLT: return true;}}}]<br>
+>;<br>
+<br>
+def COND_LE : PatLeaf <<br>
+ (cond),<br>
+ [{switch(N->get()){{default: return false;<br>
+ case ISD::SETOLE: case ISD::SETULE:<br>
+ case ISD::SETLE: return true;}}}]<br>
+>;<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Load/Store Pattern Fragments<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{<br>
+ return isGlobalLoad(dyn_cast<LoadSDNode>(N));<br>
+}]>;<br>
+<br>
+class Constants {<br>
+int TWO_PI = 0x40c90fdb;<br>
+int PI = 0x40490fdb;<br>
+int TWO_PI_INV = 0x3e22f983;<br>
+}<br>
+def CONST : Constants;<br>
+<br>
+def FP_ZERO : PatLeaf <<br>
+ (fpimm),<br>
+ [{return N->getValueAPF().isZero();}]<br>
+>;<br>
+<br>
+def FP_ONE : PatLeaf <<br>
+ (fpimm),<br>
+ [{return N->isExactlyValue(1.0);}]<br>
+>;<br>
+<br>
+let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in {<br>
+<br>
+class CLAMP <RegisterClass rc> : AMDGPUShaderInst <<br>
+ (outs rc:$dst),<br>
+ (ins rc:$src0),<br>
+ "CLAMP $dst, $src0",<br>
+ [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]<br>
+>;<br>
+<br>
+class FABS <RegisterClass rc> : AMDGPUShaderInst <<br>
+ (outs rc:$dst),<br>
+ (ins rc:$src0),<br>
+ "FABS $dst, $src0",<br>
+ [(set rc:$dst, (fabs rc:$src0))]<br>
+>;<br>
+<br>
+class FNEG <RegisterClass rc> : AMDGPUShaderInst <<br>
+ (outs rc:$dst),<br>
+ (ins rc:$src0),<br>
+ "FNEG $dst, $src0",<br>
+ [(set rc:$dst, (fneg rc:$src0))]<br>
+>;<br>
+<br>
+def SHADER_TYPE : AMDGPUShaderInst <<br>
+ (outs),<br>
+ (ins i32imm:$type),<br>
+ "SHADER_TYPE $type",<br>
+ [(int_AMDGPU_shader_type imm:$type)]<br>
+>;<br>
+<br>
+} // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1<br>
+<br>
+/* Generic helper patterns for intrinsics */<br>
+/* -------------------------------------- */<br>
+<br>
+class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,<br>
+ RegisterClass rc> : Pat <<br>
+ (fpow rc:$src0, rc:$src1),<br>
+ (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))<br>
+>;<br>
+<br>
+/* Other helper patterns */<br>
+/* --------------------- */<br>
+<br>
+/* Extract element pattern */<br>
+class Extract_Element <ValueType sub_type, ValueType vec_type,<br>
+ RegisterClass vec_class, int sub_idx,<br>
+ SubRegIndex sub_reg>: Pat<<br>
+ (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),<br>
+ (EXTRACT_SUBREG vec_class:$src, sub_reg)<br>
+>;<br>
+<br>
+/* Insert element pattern */<br>
+class Insert_Element <ValueType elem_type, ValueType vec_type,<br>
+ RegisterClass elem_class, RegisterClass vec_class,<br>
+ int sub_idx, SubRegIndex sub_reg> : Pat <<br>
+<br>
+ (vec_type (vector_insert (vec_type vec_class:$vec),<br>
+ (elem_type elem_class:$elem), sub_idx)),<br>
+ (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)<br>
+>;<br>
+<br>
+// Vector Build pattern<br>
+class Vector_Build <ValueType vecType, RegisterClass vectorClass,<br>
+ ValueType elemType, RegisterClass elemClass> : Pat <<br>
+ (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),<br>
+ (elemType elemClass:$z), (elemType elemClass:$w))),<br>
+ (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG<br>
+ (vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y),<br>
+ elemClass:$z, sel_z), elemClass:$w, sel_w)<br>
+>;<br>
+<br>
+// bitconvert pattern<br>
+class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <<br>
+ (dt (bitconvert (st rc:$src0))),<br>
+ (dt rc:$src0)<br>
+>;<br>
+<br>
+class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <<br>
+ (vt (AMDGPUdwordaddr (vt rc:$addr))),<br>
+ (vt rc:$addr)<br>
+>;<br>
+<br>
+include "R600Instructions.td"<br>
+<br>
+include "SIInstrInfo.td"<br>
+<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,62 @@<br>
+//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file defines intrinsics that are used by all hw codegen targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+let TargetPrefix = "AMDGPU", isTarget = 1 in {<br>
+<br>
+ def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;<br>
+ def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;<br>
+ def int_AMDGPU_kilp : Intrinsic<[], [], []>;<br>
+ def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_pow : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_rcp : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_AMDGPU_shader_type : Intrinsic<[], [llvm_i32_ty], []>;<br>
+}<br>
+<br>
+let TargetPrefix = "TGSI", isTarget = 1 in {<br>
+<br>
+ def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[IntrNoMem]>;<br>
+}<br>
+<br>
+include "SIIntrinsics.td"<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,77 @@<br>
+//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+<br>
+#include "AMDGPUMCInstLower.h"<br>
+#include "AMDGPUAsmPrinter.h"<br>
+#include "R600InstrInfo.h"<br>
+#include "llvm/CodeGen/MachineBasicBlock.h"<br>
+#include "llvm/CodeGen/MachineInstr.h"<br>
+#include "llvm/Constants.h"<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCStreamer.h"<br>
+#include "llvm/Support/ErrorHandling.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+AMDGPUMCInstLower::AMDGPUMCInstLower() { }<br>
+<br>
+void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {<br>
+ OutMI.setOpcode(MI->getOpcode());<br>
+<br>
+ for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {<br>
+ const MachineOperand &MO = MI->getOperand(i);<br>
+<br>
+ MCOperand MCOp;<br>
+ switch (MO.getType()) {<br>
+ default:<br>
+ llvm_unreachable("unknown operand type");<br>
+ case MachineOperand::MO_FPImmediate: {<br>
+ const APFloat &FloatValue = MO.getFPImm()->getValueAPF();<br>
+ assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&<br>
+ "Only floating point immediates are supported at the moment.");<br>
+ MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());<br>
+ break;<br>
+ }<br>
+ case MachineOperand::MO_Immediate:<br>
+ MCOp = MCOperand::CreateImm(MO.getImm());<br>
+ break;<br>
+ case MachineOperand::MO_Register:<br>
+ MCOp = MCOperand::CreateReg(MO.getReg());<br>
+ break;<br>
+ }<br>
+ OutMI.addOperand(MCOp);<br>
+ }<br>
+}<br>
+<br>
+void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {<br>
+ AMDGPUMCInstLower MCInstLowering;<br>
+<br>
+ if (MI->isBundle()) {<br>
+ const MachineBasicBlock *MBB = MI->getParent();<br>
+ MachineBasicBlock::const_instr_iterator I = MI;<br>
+ ++I;<br>
+ while (I != MBB->end() && I->isInsideBundle()) {<br>
+ MCInst MCBundleInst;<br>
+ const MachineInstr *BundledInst = I;<br>
+ MCInstLowering.lower(BundledInst, MCBundleInst);<br>
+ OutStreamer.EmitInstruction(MCBundleInst);<br>
+ ++I;<br>
+ }<br>
+ } else {<br>
+ MCInst TmpInst;<br>
+ MCInstLowering.lower(MI, TmpInst);<br>
+ OutStreamer.EmitInstruction(TmpInst);<br>
+ }<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,31 @@<br>
+//===- AMDGPUMCInstLower.h MachineInstr Lowering Interface ------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+/// \file<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPU_MCINSTLOWER_H<br>
+#define AMDGPU_MCINSTLOWER_H<br>
+<br>
+namespace llvm {<br>
+<br>
+class MCInst;<br>
+class MachineInstr;<br>
+<br>
+class AMDGPUMCInstLower {<br>
+<br>
+public:<br>
+ AMDGPUMCInstLower();<br>
+<br>
+ /// \brief Lower a MachineInstr to an MCInst<br>
+ void lower(const MachineInstr *MI, MCInst &OutMI) const;<br>
+<br>
+};<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif //AMDGPU_MCINSTLOWER_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,51 @@<br>
+//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPURegisterInfo.h"<br>
+#include "AMDGPUTargetMachine.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,<br>
+ const TargetInstrInfo &tii)<br>
+: AMDGPUGenRegisterInfo(0),<br>
+ TM(tm),<br>
+ TII(tii)<br>
+ { }<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Function handling callbacks - Functions are a seldom used feature of GPUS, so<br>
+// they are not supported at this time.<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;<br>
+<br>
+const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)<br>
+ const {<br>
+ return &CalleeSavedReg;<br>
+}<br>
+<br>
+void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,<br>
+ int SPAdj,<br>
+ RegScavenger *RS) const {<br>
+ assert(!"Subroutines not supported yet");<br>
+}<br>
+<br>
+unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {<br>
+ assert(!"Subroutines not supported yet");<br>
+ return 0;<br>
+}<br>
+<br>
+#define GET_REGINFO_TARGET_DESC<br>
+#include "AMDGPUGenRegisterInfo.inc"<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,63 @@<br>
+//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief TargetRegisterInfo interface that is implemented by all hw codegen<br>
+/// targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPUREGISTERINFO_H<br>
+#define AMDGPUREGISTERINFO_H<br>
+<br>
+#include "llvm/ADT/BitVector.h"<br>
+#include "llvm/Target/TargetRegisterInfo.h"<br>
+<br>
+#define GET_REGINFO_HEADER<br>
+#define GET_REGINFO_ENUM<br>
+#include "AMDGPUGenRegisterInfo.inc"<br>
+<br>
+namespace llvm {<br>
+<br>
+class AMDGPUTargetMachine;<br>
+class TargetInstrInfo;<br>
+<br>
+struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {<br>
+ TargetMachine &TM;<br>
+ const TargetInstrInfo &TII;<br>
+ static const uint16_t CalleeSavedReg;<br>
+<br>
+ AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);<br>
+<br>
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const {<br>
+ assert(!"Unimplemented"); return BitVector();<br>
+ }<br>
+<br>
+ /// \param RC is an AMDIL reg class.<br>
+ ///<br>
+ /// \returns The ISA reg class that is equivalent to \p RC.<br>
+ virtual const TargetRegisterClass * getISARegClass(<br>
+ const TargetRegisterClass * RC) const {<br>
+ assert(!"Unimplemented"); return NULL;<br>
+ }<br>
+<br>
+ virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {<br>
+ assert(!"Unimplemented"); return NULL;<br>
+ }<br>
+<br>
+ const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;<br>
+ void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,<br>
+ RegScavenger *RS) const;<br>
+ unsigned getFrameRegister(const MachineFunction &MF) const;<br>
+<br>
+};<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif // AMDIDSAREGISTERINFO_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.td Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,22 @@<br>
+//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// Tablegen register definitions common to all hw codegen targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+let Namespace = "AMDGPU" in {<br>
+ def sel_x : SubRegIndex;<br>
+ def sel_y : SubRegIndex;<br>
+ def sel_z : SubRegIndex;<br>
+ def sel_w : SubRegIndex;<br>
+}<br>
+<br>
+include "R600RegisterInfo.td"<br>
+include "SIRegisterInfo.td"<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,87 @@<br>
+//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief Implements the AMDGPU specific subclass of TargetSubtarget.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPUSubtarget.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#define GET_SUBTARGETINFO_ENUM<br>
+#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
+#include "AMDGPUGenSubtargetInfo.inc"<br>
+<br>
+AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :<br>
+ AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) {<br>
+ InstrItins = getInstrItineraryForCPU(CPU);<br>
+<br>
+ memset(CapsOverride, 0, sizeof(*CapsOverride)<br>
+ * AMDGPUDeviceInfo::MaxNumberCapabilities);<br>
+ // Default card<br>
+ StringRef GPU = CPU;<br>
+ Is64bit = false;<br>
+ DefaultSize[0] = 64;<br>
+ DefaultSize[1] = 1;<br>
+ DefaultSize[2] = 1;<br>
+ ParseSubtargetFeatures(GPU, FS);<br>
+ DevName = GPU;<br>
+ Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);<br>
+}<br>
+<br>
+AMDGPUSubtarget::~AMDGPUSubtarget() {<br>
+ delete Device;<br>
+}<br>
+<br>
+bool<br>
+AMDGPUSubtarget::isOverride(AMDGPUDeviceInfo::Caps caps) const {<br>
+ assert(caps < AMDGPUDeviceInfo::MaxNumberCapabilities &&<br>
+ "Caps index is out of bounds!");<br>
+ return CapsOverride[caps];<br>
+}<br>
+bool<br>
+AMDGPUSubtarget::is64bit() const {<br>
+ return Is64bit;<br>
+}<br>
+bool<br>
+AMDGPUSubtarget::isTargetELF() const {<br>
+ return false;<br>
+}<br>
+size_t<br>
+AMDGPUSubtarget::getDefaultSize(uint32_t dim) const {<br>
+ if (dim > 3) {<br>
+ return 1;<br>
+ } else {<br>
+ return DefaultSize[dim];<br>
+ }<br>
+}<br>
+<br>
+std::string<br>
+AMDGPUSubtarget::getDataLayout() const {<br>
+ if (!Device) {<br>
+ return std::string("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"<br>
+ "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"<br>
+ "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"<br>
+ "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"<br>
+ "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");<br>
+ }<br>
+ return Device->getDataLayout();<br>
+}<br>
+<br>
+std::string<br>
+AMDGPUSubtarget::getDeviceName() const {<br>
+ return DevName;<br>
+}<br>
+const AMDGPUDevice *<br>
+AMDGPUSubtarget::device() const {<br>
+ return Device;<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,65 @@<br>
+//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//==-----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief AMDGPU specific subclass of TargetSubtarget.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPUSUBTARGET_H<br>
+#define AMDGPUSUBTARGET_H<br>
+#include "AMDILDevice.h"<br>
+#include "llvm/ADT/StringExtras.h"<br>
+#include "llvm/ADT/StringRef.h"<br>
+#include "llvm/Target/TargetSubtargetInfo.h"<br>
+<br>
+#define GET_SUBTARGETINFO_HEADER<br>
+#include "AMDGPUGenSubtargetInfo.inc"<br>
+<br>
+#define MAX_CB_SIZE (1 << 16)<br>
+<br>
+namespace llvm {<br>
+<br>
+class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {<br>
+private:<br>
+ bool CapsOverride[AMDGPUDeviceInfo::MaxNumberCapabilities];<br>
+ const AMDGPUDevice *Device;<br>
+ size_t DefaultSize[3];<br>
+ std::string DevName;<br>
+ bool Is64bit;<br>
+ bool Is32on64bit;<br>
+ bool DumpCode;<br>
+ bool R600ALUInst;<br>
+<br>
+ InstrItineraryData InstrItins;<br>
+<br>
+public:<br>
+ AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);<br>
+ virtual ~AMDGPUSubtarget();<br>
+<br>
+ const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }<br>
+ virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);<br>
+<br>
+ bool isOverride(AMDGPUDeviceInfo::Caps) const;<br>
+ bool is64bit() const;<br>
+<br>
+ // Helper functions to simplify if statements<br>
+ bool isTargetELF() const;<br>
+ const AMDGPUDevice* device() const;<br>
+ std::string getDataLayout() const;<br>
+ std::string getDeviceName() const;<br>
+ virtual size_t getDefaultSize(uint32_t dim) const;<br>
+ bool dumpCode() const { return DumpCode; }<br>
+ bool r600ALUEncoding() const { return R600ALUInst; }<br>
+<br>
+};<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif // AMDGPUSUBTARGET_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,141 @@<br>
+//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief The AMDGPU target machine contains all of the hardware specific<br>
+/// information needed to emit code for R600 and SI GPUs.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AMDGPUTargetMachine.h"<br>
+#include "AMDGPU.h"<br>
+#include "R600ISelLowering.h"<br>
+#include "R600InstrInfo.h"<br>
+#include "SIISelLowering.h"<br>
+#include "SIInstrInfo.h"<br>
+#include "llvm/Analysis/Passes.h"<br>
+#include "llvm/Analysis/Verifier.h"<br>
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"<br>
+#include "llvm/CodeGen/MachineModuleInfo.h"<br>
+#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/MC/MCAsmInfo.h"<br>
+#include "llvm/PassManager.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+#include "llvm/Support/raw_os_ostream.h"<br>
+#include "llvm/Transforms/IPO.h"<br>
+#include "llvm/Transforms/Scalar.h"<br>
+#include <llvm/CodeGen/Passes.h><br>
+<br>
+using namespace llvm;<br>
+<br>
+extern "C" void LLVMInitializeR600Target() {<br>
+ // Register the target<br>
+ RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);<br>
+}<br>
+<br>
+AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,<br>
+ StringRef CPU, StringRef FS,<br>
+ TargetOptions Options,<br>
+ Reloc::Model RM, CodeModel::Model CM,<br>
+ CodeGenOpt::Level OptLevel<br>
+)<br>
+:<br>
+ LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),<br>
+ Subtarget(TT, CPU, FS),<br>
+ Layout(Subtarget.getDataLayout()),<br>
+ FrameLowering(TargetFrameLowering::StackGrowsUp,<br>
+ Subtarget.device()->getStackAlignment(), 0),<br>
+ IntrinsicInfo(this),<br>
+ InstrItins(&Subtarget.getInstrItineraryData()) {<br>
+ // TLInfo uses InstrInfo so it must be initialized after.<br>
+ if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {<br>
+ InstrInfo = new R600InstrInfo(*this);<br>
+ TLInfo = new R600TargetLowering(*this);<br>
+ } else {<br>
+ InstrInfo = new SIInstrInfo(*this);<br>
+ TLInfo = new SITargetLowering(*this);<br>
+ }<br>
+}<br>
+<br>
+AMDGPUTargetMachine::~AMDGPUTargetMachine() {<br>
+}<br>
+<br>
+namespace {<br>
+class AMDGPUPassConfig : public TargetPassConfig {<br>
+public:<br>
+ AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)<br>
+ : TargetPassConfig(TM, PM) {}<br>
+<br>
+ AMDGPUTargetMachine &getAMDGPUTargetMachine() const {<br>
+ return getTM<AMDGPUTargetMachine>();<br>
+ }<br>
+<br>
+ virtual bool addPreISel();<br>
+ virtual bool addInstSelector();<br>
+ virtual bool addPreRegAlloc();<br>
+ virtual bool addPostRegAlloc();<br>
+ virtual bool addPreSched2();<br>
+ virtual bool addPreEmitPass();<br>
+};<br>
+} // End of anonymous namespace<br>
+<br>
+TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {<br>
+ return new AMDGPUPassConfig(this, PM);<br>
+}<br>
+<br>
+bool<br>
+AMDGPUPassConfig::addPreISel() {<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUPassConfig::addInstSelector() {<br>
+ addPass(createAMDGPUPeepholeOpt(*TM));<br>
+ addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUPassConfig::addPreRegAlloc() {<br>
+ const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();<br>
+<br>
+ if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {<br>
+ addPass(createSIAssignInterpRegsPass(*TM));<br>
+ }<br>
+ addPass(createAMDGPUConvertToISAPass(*TM));<br>
+ if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {<br>
+ addPass(createSIFixSGPRLivenessPass(*TM));<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUPassConfig::addPostRegAlloc() {<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUPassConfig::addPreSched2() {<br>
+<br>
+ addPass(&IfConverterID);<br>
+ return false;<br>
+}<br>
+<br>
+bool AMDGPUPassConfig::addPreEmitPass() {<br>
+ addPass(createAMDGPUCFGPreparationPass(*TM));<br>
+ addPass(createAMDGPUCFGStructurizerPass(*TM));<br>
+<br>
+ const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();<br>
+ if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {<br>
+ addPass(createR600ExpandSpecialInstrsPass(*TM));<br>
+ addPass(&FinalizeMachineBundlesID);<br>
+ } else {<br>
+ addPass(createSILowerLiteralConstantsPass(*TM));<br>
+ addPass(createSILowerControlFlowPass(*TM));<br>
+ }<br>
+<br>
+ return false;<br>
+}<br>
+<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,70 @@<br>
+//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef AMDGPU_TARGET_MACHINE_H<br>
+#define AMDGPU_TARGET_MACHINE_H<br>
+<br>
+#include "AMDGPUInstrInfo.h"<br>
+#include "AMDGPUSubtarget.h"<br>
+#include "AMDILFrameLowering.h"<br>
+#include "AMDILIntrinsicInfo.h"<br>
+#include "R600ISelLowering.h"<br>
+#include "llvm/ADT/OwningPtr.h"<br>
+#include "llvm/DataLayout.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);<br>
+<br>
+class AMDGPUTargetMachine : public LLVMTargetMachine {<br>
+<br>
+ AMDGPUSubtarget Subtarget;<br>
+ const DataLayout Layout;<br>
+ AMDGPUFrameLowering FrameLowering;<br>
+ AMDGPUIntrinsicInfo IntrinsicInfo;<br>
+ const AMDGPUInstrInfo * InstrInfo;<br>
+ AMDGPUTargetLowering * TLInfo;<br>
+ const InstrItineraryData* InstrItins;<br>
+<br>
+public:<br>
+ AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,<br>
+ StringRef CPU,<br>
+ TargetOptions Options,<br>
+ Reloc::Model RM, CodeModel::Model CM,<br>
+ CodeGenOpt::Level OL);<br>
+ ~AMDGPUTargetMachine();<br>
+ virtual const AMDGPUFrameLowering* getFrameLowering() const {<br>
+ return &FrameLowering;<br>
+ }<br>
+ virtual const AMDGPUIntrinsicInfo* getIntrinsicInfo() const {<br>
+ return &IntrinsicInfo;<br>
+ }<br>
+ virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;}<br>
+ virtual const AMDGPUSubtarget *getSubtargetImpl() const {return &Subtarget; }<br>
+ virtual const AMDGPURegisterInfo *getRegisterInfo() const {<br>
+ return &InstrInfo->getRegisterInfo();<br>
+ }<br>
+ virtual AMDGPUTargetLowering * getTargetLowering() const {<br>
+ return TLInfo;<br>
+ }<br>
+ virtual const InstrItineraryData* getInstrItineraryData() const {<br>
+ return InstrItins;<br>
+ }<br>
+ virtual const DataLayout* getDataLayout() const { return &Layout; }<br>
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);<br>
+};<br>
+<br>
+} // End namespace llvm<br>
+<br>
+#endif // AMDGPU_TARGET_MACHINE_H<br>
<br>
Added: llvm/trunk/lib/Target/R600/AMDIL.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDIL.h?rev=169915&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDIL.h?rev=169915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDIL.h (added)<br>
+++ llvm/trunk/lib/Target/R600/AMDIL.h Tue Dec 11 15:25:42 2012<br>
@@ -0,0 +1,106 @@<br>
+//===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This ...<br><br>[Message clipped] </blockquote></div><br></div>