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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoPlainText>Hello Hao,<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText style='margin-left:.25in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>The tests need a full ‘aarch64-linux-gnu’ triple to avoid breaking on unsupported platforms.<o:p></o:p></p><p class=MsoPlainText>So in the tests replace -march=aarch64 with -mtriple=aarch64-none-linux-gnu and replace -triple=aarch64 with -triple aarch64-none-linux-gnu<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText style='margin-left:.25in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>The use of H as a new size modifier<o:p></o:p></p><p class=MsoPlainText>It seems what you need is just a condition to skip adding ‘q’ to the intrinsics name even when the type is classified as Q, correct?<o:p></o:p></p><p class=MsoPlainText>Something like adding a record field “isShiftPart2” or some more generic field so it can be reused by other intrinsics that have similar naming requirement.<o:p></o:p></p><p class=MsoPlainText>It will require a bit more clang changes, but it will be clearer what you are trying to do.<o:p></o:p></p><p class=MsoPlainText>What do you think?<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Thanks,<o:p></o:p></p><p class=MsoPlainText>Ana.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Hao Liu<br><b>Sent:</b> Friday, August 09, 2013 1:20 PM<br><b>To:</b> tnorthover@apple.com; llvm-commits@cs.uiuc.edu<br><b>Cc:</b> Jiangning Liu<br><b>Subject:</b> [PATCH]Clang and AArch64 backend patches to support sshll/ushll instructions<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoPlainText>Hello Tim and LLVM reviewers,<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoNormal>I have created a patch to implement sshll and ushll instructions in AArch64 backend and support vshll and vmovl ACLE functions in Clang. The reason I need to upstream this patch is that the work of my colleague depends on these instructions.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The implementation of this patch follows the existing code of AArch64 NEON instructions and ARM target. The vmovl ACLE functions are also implemented, as they are compiled into sshll and ushll instructions.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Tim (and anyone else interested), could you review the patches?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<o:p></o:p></p><p class=MsoNormal>-Hao<o:p></o:p></p></div></body></html>