<div dir="ltr">This function became unused after r<span style="font-family:arial,sans-serif;font-size:13px">187828</span>.<div><br></div><div>Thank you for fixing this.</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">
On Tue, Aug 6, 2013 at 5:27 PM, David Blaikie <span dir="ltr"><<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5">On Wed, Jan 16, 2013 at 4:28 PM, Jack Carter <<a href="mailto:jcarter@mips.com">jcarter@mips.com</a>> wrote:<br>
> Author: jacksprat<br>
> Date: Wed Jan 16 18:28:20 2013<br>
> New Revision: 172685<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=172685&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=172685&view=rev</a><br>
> Log:<br>
> This is a resubmittal. For some reason it broke the bots yesterday<br>
> but I cannot reproduce the problem and have scrubed my sources and<br>
> even tested with llvm-lit -v --vg.<br>
><br>
> The Mips RDHWR (Read Hardware Register) instruction was not<br>
> tested for assembler or dissassembler consumption. This patch<br>
> adds that functionality.<br>
><br>
> Contributer: Vladimir Medic<br>
><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
> llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td<br>
> llvm/trunk/test/MC/Disassembler/Mips/mips32.txt<br>
> llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt<br>
> llvm/trunk/test/MC/Mips/mips-alu-instructions.s<br>
> llvm/trunk/test/MC/Mips/mips64-alu-instructions.s<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jan 16 18:28:20 2013<br>
> @@ -1045,6 +1045,9 @@<br>
> MipsAsmParser::OperandMatchResultTy<br>
> MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {<br>
><br>
> + if (isMips64())<br>
> + return MatchOperand_NoMatch;<br>
> +<br>
> // if the first token is not '$' we have error<br>
> if (Parser.getTok().isNot(AsmToken::Dollar))<br>
> return MatchOperand_NoMatch;<br>
> @@ -1071,6 +1074,9 @@<br>
><br>
> MipsAsmParser::OperandMatchResultTy<br>
> MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {<br>
> +<br>
> + if (!isMips64())<br>
> + return MatchOperand_NoMatch;<br>
> //if the first token is not '$' we have error<br>
> if (Parser.getTok().isNot(AsmToken::Dollar))<br>
> return MatchOperand_NoMatch;<br>
> @@ -1088,7 +1094,7 @@<br>
><br>
> MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,<br>
> Parser.getTok().getLoc());<br>
> - op->setRegKind(MipsOperand::Kind_HWRegs);<br>
> + op->setRegKind(MipsOperand::Kind_HW64Regs);<br>
> Operands.push_back(op);<br>
><br>
> Parser.Lex(); // Eat reg number<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Jan 16 18:28:20 2013<br>
> @@ -128,6 +128,11 @@<br>
> uint64_t Address,<br>
> const void *Decoder);<br>
><br>
> +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,<br>
> + unsigned Insn,<br>
> + uint64_t Address,<br>
> + const void *Decoder);<br>
> +<br>
<br>
</div></div>This function was/is unused, I removed it in r187838 to clean up the<br>
Clang -Werror build.<br>
<div class="HOEnZb"><div class="h5"><br>
> static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,<br>
> unsigned RegNo,<br>
> uint64_t Address,<br>
> @@ -454,6 +459,17 @@<br>
> return MCDisassembler::Success;<br>
> }<br>
><br>
> +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,<br>
> + unsigned RegNo,<br>
> + uint64_t Address,<br>
> + const void *Decoder) {<br>
> + //Currently only hardware register 29 is supported<br>
> + if (RegNo != 29)<br>
> + return MCDisassembler::Fail;<br>
> + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));<br>
> + return MCDisassembler::Success;<br>
> +}<br>
> +<br>
> static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,<br>
> unsigned RegNo,<br>
> uint64_t Address,<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Jan 16 18:28:20 2013<br>
> @@ -373,6 +373,6 @@<br>
> let ParserMatchClass = HWRegsAsmOperand;<br>
> }<br>
><br>
> -def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {<br>
> +def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {<br>
> let ParserMatchClass = HW64RegsAsmOperand;<br>
> }<br>
><br>
> Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)<br>
> +++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Wed Jan 16 18:28:20 2013<br>
> @@ -404,3 +404,9 @@<br>
><br>
> # CHECK: xori $9, $6, 17767<br>
> 0x38 0xc9 0x45 0x67<br>
> +<br>
> +# CHECK: .set push<br>
> +# CHECK: .set mips32r2<br>
> +# CHECK: rdhwr $5, $29<br>
> +# CHECK: .set pop<br>
> +0x7c 0x05 0xe8 0x3b<br>
><br>
> Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)<br>
> +++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Wed Jan 16 18:28:20 2013<br>
> @@ -404,3 +404,9 @@<br>
><br>
> # CHECK: xori $9, $6, 17767<br>
> 0x67 0x45 0xc9 0x38<br>
> +<br>
> +# CHECK: .set push<br>
> +# CHECK: .set mips32r2<br>
> +# CHECK: rdhwr $5, $29<br>
> +# CHECK: .set pop<br>
> +0x3b 0xe8 0x05 0x7c<br>
><br>
> Modified: llvm/trunk/test/MC/Mips/mips-alu-instructions.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/Mips/mips-alu-instructions.s (original)<br>
> +++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s Wed Jan 16 18:28:20 2013<br>
> @@ -81,6 +81,10 @@<br>
> # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]<br>
> # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]<br>
> # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01]<br>
> +# CHECK: .set push<br>
> +# CHECK: .set mips32r2<br>
> +# CHECK: rdhwr $5, $29<br>
> +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]<br>
> add $9,$6,$7<br>
> add $9,$6,17767<br>
> addu $9,$6,-15001<br>
> @@ -98,3 +102,4 @@<br>
> neg $6,$7<br>
> negu $6,$7<br>
> move $7,$8<br>
> + rdhwr $5, $29<br>
><br>
> Modified: llvm/trunk/test/MC/Mips/mips64-alu-instructions.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/Mips/mips64-alu-instructions.s (original)<br>
> +++ llvm/trunk/test/MC/Mips/mips64-alu-instructions.s Wed Jan 16 18:28:20 2013<br>
> @@ -78,6 +78,11 @@<br>
> # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]<br>
> # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]<br>
> # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]<br>
> +# CHECK: .set push<br>
> +# CHECK: .set mips32r2<br>
> +# CHECK: rdhwr $5, $29<br>
> +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]<br>
> +<br>
> dadd $9,$6,$7<br>
> dadd $9,$6,17767<br>
> daddu $9,$6,-15001<br>
> @@ -92,3 +97,4 @@<br>
> multu $3,$5<br>
> dsubu $4,$3,$5<br>
> move $7,$8<br>
> + rdhwr $5, $29<br>
><br>
><br>
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</div></div></blockquote></div><br></div>