<div dir="ltr">Internally, we are using an older version of TableGen (before the addition of the newer syntax) and I want to maintain as much code sharing as possible. I would love to rewrite all of our rules to take advantage of the newer type-based syntax instead of the register-class-based syntax, but I can't until we use a newer TableGen internally.</div>
<div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Aug 6, 2013 at 10:41 AM, Tom Stellard <span dir="ltr"><<a href="mailto:tom@stellard.net" target="_blank">tom@stellard.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5">On Tue, Aug 06, 2013 at 02:13:34PM -0000, Justin Holewinski wrote:<br>
> Author: jholewinski<br>
> Date: Tue Aug 6 09:13:34 2013<br>
> New Revision: 187800<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=187800&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=187800&view=rev</a><br>
> Log:<br>
> [NVPTX] Add missing patterns for i1 [s,u]int_to_fp<br>
><br>
> Added:<br>
> llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll<br>
> Modified:<br>
> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td<br>
><br>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=187800&r1=187799&r2=187800&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=187800&r1=187799&r2=187800&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td Tue Aug 6 09:13:34 2013<br>
> @@ -2208,6 +2208,17 @@ defm STV_f64 : ST_VEC<Float64Regs>;<br>
><br>
> //---- Conversion ----<br>
><br>
> +class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,<br>
> + NVPTXRegClass regclassOut> :<br>
> + NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),<br>
> + !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),<br>
> + [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;<br>
> +<br>
> +def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;<br>
> +def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;<br>
> +def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;<br>
> +def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;<br>
> +<br>
> // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where<br>
> // we cannot specify floating-point literals in isel patterns. Therefore, we<br>
> // use an integer selp to select either 1 or 0 and then cvt to floating-point.<br>
> @@ -2254,6 +2265,8 @@ def : Pat<(f64 (uint_to_fp Int64Regs:$a)<br>
><br>
><br>
> // f32 -> sint<br>
> +def : Pat<(i1 (fp_to_sint Float32Regs:$a)),<br>
> + (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;<br>
<br>
</div></div>You can define patterns with types instead of registers class and<br>
you don't need the type in the result pattern, so the above could be<br>
simplified as:<br>
<br>
def : Pat<(i1 (fp_to_sint f32:$a)),<br>
(SETP_b32ri (BITCONVERT_32_F2I $a), 0, CmpEQ)>;<br>
<br>
-Tom<br>
<div class="HOEnZb"><div class="h5"><br>
> def : Pat<(i16 (fp_to_sint Float32Regs:$a)),<br>
> (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;<br>
> def : Pat<(i16 (fp_to_sint Float32Regs:$a)),<br>
> @@ -2268,6 +2281,8 @@ def : Pat<(i64 (fp_to_sint Float32Regs:$<br>
> (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;<br>
><br>
> // f32 -> uint<br>
> +def : Pat<(i1 (fp_to_uint Float32Regs:$a)),<br>
> + (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;<br>
> def : Pat<(i16 (fp_to_uint Float32Regs:$a)),<br>
> (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;<br>
> def : Pat<(i16 (fp_to_uint Float32Regs:$a)),<br>
> @@ -2282,6 +2297,8 @@ def : Pat<(i64 (fp_to_uint Float32Regs:$<br>
> (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;<br>
><br>
> // f64 -> sint<br>
> +def : Pat<(i1 (fp_to_sint Float64Regs:$a)),<br>
> + (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;<br>
> def : Pat<(i16 (fp_to_sint Float64Regs:$a)),<br>
> (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;<br>
> def : Pat<(i32 (fp_to_sint Float64Regs:$a)),<br>
> @@ -2290,6 +2307,8 @@ def : Pat<(i64 (fp_to_sint Float64Regs:$<br>
> (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;<br>
><br>
> // f64 -> uint<br>
> +def : Pat<(i1 (fp_to_uint Float64Regs:$a)),<br>
> + (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;<br>
> def : Pat<(i16 (fp_to_uint Float64Regs:$a)),<br>
> (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;<br>
> def : Pat<(i32 (fp_to_uint Float64Regs:$a)),<br>
> @@ -2397,17 +2416,6 @@ def : Pat<(select Int32Regs:$pred, Float<br>
> (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;<br>
><br>
><br>
> -class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,<br>
> - NVPTXRegClass regclassOut> :<br>
> - NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),<br>
> - !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),<br>
> - [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;<br>
> -<br>
> -def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;<br>
> -def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;<br>
> -def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;<br>
> -def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;<br>
> -<br>
> // pack a set of smaller int registers to a larger int register<br>
> def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),<br>
> (ins Int16Regs:$s1, Int16Regs:$s2,<br>
><br>
> Added: llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll?rev=187800&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll?rev=187800&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll Tue Aug 6 09:13:34 2013<br>
> @@ -0,0 +1,37 @@<br>
> +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
> +<br>
> +; CHECK-LABEL: foo<br>
> +; CHECK: setp<br>
> +; CHECK: selp<br>
> +; CHECK: cvt.rn.f32.u32<br>
> +define float @foo(i1 %a) {<br>
> + %ret = uitofp i1 %a to float<br>
> + ret float %ret<br>
> +}<br>
> +<br>
> +; CHECK-LABEL: foo2<br>
> +; CHECK: setp<br>
> +; CHECK: selp<br>
> +; CHECK: cvt.rn.f32.s32<br>
> +define float @foo2(i1 %a) {<br>
> + %ret = sitofp i1 %a to float<br>
> + ret float %ret<br>
> +}<br>
> +<br>
> +; CHECK-LABEL: foo3<br>
> +; CHECK: setp<br>
> +; CHECK: selp<br>
> +; CHECK: cvt.rn.f64.u32<br>
> +define double @foo3(i1 %a) {<br>
> + %ret = uitofp i1 %a to double<br>
> + ret double %ret<br>
> +}<br>
> +<br>
> +; CHECK-LABEL: foo4<br>
> +; CHECK: setp<br>
> +; CHECK: selp<br>
> +; CHECK: cvt.rn.f64.s32<br>
> +define double @foo4(i1 %a) {<br>
> + %ret = sitofp i1 %a to double<br>
> + ret double %ret<br>
> +}<br>
><br>
><br>
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</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div>
</div>