<div dir="ltr">FYI, as you're not on IRC and may not have seen the bot's email -- this seems to have broken all of the builds...<div><br></div><div><a href="http://lab.llvm.org:8011/builders/llvm-x86_64-ubuntu/builds/9987">http://lab.llvm.org:8011/builders/llvm-x86_64-ubuntu/builds/9987</a><br>
</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Sat, Jul 13, 2013 at 9:42 PM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Sat Jul 13 23:42:23 2013<br>
New Revision: 186274<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=186274&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=186274&view=rev</a><br>
Log:<br>
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h<br>
llvm/trunk/include/llvm/CodeGen/CallingConvLower.h<br>
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h<br>
llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp<br>
llvm/trunk/lib/Analysis/DependenceAnalysis.cpp<br>
llvm/trunk/lib/Analysis/ProfileDataLoader.cpp<br>
llvm/trunk/lib/CodeGen/CallingConvLower.cpp<br>
llvm/trunk/lib/CodeGen/MachineCSE.cpp<br>
llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp<br>
llvm/trunk/lib/CodeGen/MachineSink.cpp<br>
llvm/trunk/lib/CodeGen/PrologEpilogInserter.h<br>
llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp<br>
llvm/trunk/lib/CodeGen/StackSlotColoring.cpp<br>
llvm/trunk/lib/CodeGen/TailDuplication.cpp<br>
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp<br>
llvm/trunk/lib/IR/Metadata.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp<br>
llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp<br>
llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h<br>
llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp<br>
llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp<br>
llvm/trunk/lib/Target/R600/R600InstrInfo.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp<br>
llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp<br>
llvm/trunk/lib/Transforms/Scalar/SCCP.cpp<br>
llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp<br>
llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp<br>
llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp<br>
llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp<br>
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp<br>
llvm/trunk/utils/TableGen/CodeGenRegisters.h<br>
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h (original)<br>
+++ llvm/trunk/include/llvm/Analysis/DependenceAnalysis.h Sat Jul 13 23:42:23 2013<br>
@@ -849,7 +849,7 @@ namespace llvm {<br>
bool propagate(const SCEV *&Src,<br>
const SCEV *&Dst,<br>
SmallBitVector &Loops,<br>
- SmallVector<Constraint, 4> &Constraints,<br>
+ SmallVectorImpl<Constraint> &Constraints,<br>
bool &Consistent);<br>
<br>
/// propagateDistance - Attempt to propagate a distance<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Sat Jul 13 23:42:23 2013<br>
@@ -158,7 +158,7 @@ private:<br>
MachineFunction &MF;<br>
const TargetMachine &TM;<br>
const TargetRegisterInfo &TRI;<br>
- SmallVector<CCValAssign, 16> &Locs;<br>
+ SmallVectorImpl<CCValAssign> &Locs;<br>
LLVMContext &Context;<br>
<br>
unsigned StackOffset;<br>
@@ -219,7 +219,7 @@ protected:<br>
<br>
public:<br>
CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,<br>
- const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,<br>
+ const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,<br>
LLVMContext &C);<br>
<br>
void addLoc(const CCValAssign &V) {<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Sat Jul 13 23:42:23 2013<br>
@@ -539,7 +539,7 @@ public:<br>
/// NOTE: This is still very expensive. Use carefully.<br>
bool hasPredecessorHelper(const SDNode *N,<br>
SmallPtrSet<const SDNode *, 32> &Visited,<br>
- SmallVector<const SDNode *, 16> &Worklist) const;<br>
+ SmallVectorImpl<const SDNode *> &Worklist) const;<br>
<br>
/// getNumOperands - Return the number of values used by this operation.<br>
///<br>
<br>
Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sat Jul 13 23:42:23 2013<br>
@@ -857,8 +857,8 @@ BasicAliasAnalysis::getModRefInfo(Immuta<br>
return ModRefResult(AliasAnalysis::getModRefInfo(CS, Loc) & Min);<br>
}<br>
<br>
-static bool areVarIndicesEqual(SmallVector<VariableGEPIndex, 4> &Indices1,<br>
- SmallVector<VariableGEPIndex, 4> &Indices2) {<br>
+static bool areVarIndicesEqual(SmallVectorImpl<VariableGEPIndex> &Indices1,<br>
+ SmallVectorImpl<VariableGEPIndex> &Indices2) {<br>
unsigned Size1 = Indices1.size();<br>
unsigned Size2 = Indices2.size();<br>
<br>
<br>
Modified: llvm/trunk/lib/Analysis/DependenceAnalysis.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DependenceAnalysis.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DependenceAnalysis.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/DependenceAnalysis.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/DependenceAnalysis.cpp Sat Jul 13 23:42:23 2013<br>
@@ -2977,7 +2977,7 @@ const SCEV *DependenceAnalysis::addToCoe<br>
bool DependenceAnalysis::propagate(const SCEV *&Src,<br>
const SCEV *&Dst,<br>
SmallBitVector &Loops,<br>
- SmallVector<Constraint, 4> &Constraints,<br>
+ SmallVectorImpl<Constraint> &Constraints,<br>
bool &Consistent) {<br>
bool Result = false;<br>
for (int LI = Loops.find_first(); LI >= 0; LI = Loops.find_next(LI)) {<br>
<br>
Modified: llvm/trunk/lib/Analysis/ProfileDataLoader.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileDataLoader.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileDataLoader.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/ProfileDataLoader.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/ProfileDataLoader.cpp Sat Jul 13 23:42:23 2013<br>
@@ -76,7 +76,7 @@ static unsigned ReadProfilingNumEntries(<br>
/// packet and then accumulate the entries into 'Data'.<br>
static void ReadProfilingBlock(const char *ToolName, FILE *F,<br>
bool ShouldByteSwap,<br>
- SmallVector<unsigned, 32> &Data) {<br>
+ SmallVectorImpl<unsigned> &Data) {<br>
// Read the number of entries...<br>
unsigned NumEntries = ReadProfilingNumEntries(ToolName, F, ShouldByteSwap);<br>
<br>
@@ -99,7 +99,7 @@ static void ReadProfilingBlock(const cha<br>
/// run with when the current profiling data packet(s) were generated.<br>
static void ReadProfilingArgBlock(const char *ToolName, FILE *F,<br>
bool ShouldByteSwap,<br>
- SmallVector<std::string, 1> &CommandLines) {<br>
+ SmallVectorImpl<std::string> &CommandLines) {<br>
// Read the number of bytes ...<br>
unsigned ArgLength = ReadProfilingNumEntries(ToolName, F, ShouldByteSwap);<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Sat Jul 13 23:42:23 2013<br>
@@ -24,7 +24,7 @@<br>
using namespace llvm;<br>
<br>
CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf,<br>
- const TargetMachine &tm, SmallVector<CCValAssign, 16> &locs,<br>
+ const TargetMachine &tm, SmallVectorImpl<CCValAssign> &locs,<br>
LLVMContext &C)<br>
: CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm),<br>
TRI(*TM.getRegisterInfo()), Locs(locs), Context(C),<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Sat Jul 13 23:42:23 2013<br>
@@ -84,11 +84,11 @@ namespace {<br>
bool hasLivePhysRegDefUses(const MachineInstr *MI,<br>
const MachineBasicBlock *MBB,<br>
SmallSet<unsigned,8> &PhysRefs,<br>
- SmallVector<unsigned,2> &PhysDefs,<br>
+ SmallVectorImpl<unsigned> &PhysDefs,<br>
bool &PhysUseDef) const;<br>
bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,<br>
SmallSet<unsigned,8> &PhysRefs,<br>
- SmallVector<unsigned,2> &PhysDefs,<br>
+ SmallVectorImpl<unsigned> &PhysDefs,<br>
bool &NonLocal) const;<br>
bool isCSECandidate(MachineInstr *MI);<br>
bool isProfitableToCSE(unsigned CSReg, unsigned Reg,<br>
@@ -193,7 +193,7 @@ MachineCSE::isPhysDefTriviallyDead(unsig<br>
bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,<br>
const MachineBasicBlock *MBB,<br>
SmallSet<unsigned,8> &PhysRefs,<br>
- SmallVector<unsigned,2> &PhysDefs,<br>
+ SmallVectorImpl<unsigned> &PhysDefs,<br>
bool &PhysUseDef) const{<br>
// First, add all uses to PhysRefs.<br>
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br>
@@ -244,7 +244,7 @@ bool MachineCSE::hasLivePhysRegDefUses(c<br>
<br>
bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,<br>
SmallSet<unsigned,8> &PhysRefs,<br>
- SmallVector<unsigned,2> &PhysDefs,<br>
+ SmallVectorImpl<unsigned> &PhysDefs,<br>
bool &NonLocal) const {<br>
// For now conservatively returns false if the common subexpression is<br>
// not in the same basic block as the given instruction. The only exception<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Sat Jul 13 23:42:23 2013<br>
@@ -77,7 +77,7 @@ unsigned MachineSSAUpdater::GetValueAtEn<br>
<br>
static<br>
unsigned LookForIdenticalPHI(MachineBasicBlock *BB,<br>
- SmallVector<std::pair<MachineBasicBlock*, unsigned>, 8> &PredValues) {<br>
+ SmallVectorImpl<std::pair<MachineBasicBlock*, unsigned> > &PredValues) {<br>
if (BB->empty())<br>
return 0;<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Sat Jul 13 23:42:23 2013<br>
@@ -394,7 +394,7 @@ static bool AvoidsSinking(MachineInstr *<br>
/// collectDebgValues - Scan instructions following MI and collect any<br>
/// matching DBG_VALUEs.<br>
static void collectDebugValues(MachineInstr *MI,<br>
- SmallVector<MachineInstr *, 2> & DbgValues) {<br>
+ SmallVectorImpl<MachineInstr *> &DbgValues) {<br>
DbgValues.clear();<br>
if (!MI->getOperand(0).isReg())<br>
return;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.h (original)<br>
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.h Sat Jul 13 23:42:23 2013<br>
@@ -112,13 +112,13 @@ namespace llvm {<br>
bool calcAvailInOut(MachineBasicBlock* MBB);<br>
void calculateAnticAvail(MachineFunction &Fn);<br>
bool addUsesForMEMERegion(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4>& blks);<br>
- bool addUsesForTopLevelLoops(SmallVector<MachineBasicBlock*, 4>& blks);<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks);<br>
+ bool addUsesForTopLevelLoops(SmallVectorImpl<MachineBasicBlock *> &blks);<br>
bool calcSpillPlacements(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4> &blks,<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks,<br>
CSRegBlockMap &prevSpills);<br>
bool calcRestorePlacements(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4> &blks,<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks,<br>
CSRegBlockMap &prevRestores);<br>
void placeSpillsAndRestores(MachineFunction &Fn);<br>
void placeCSRSpillsAndRestores(MachineFunction &Fn);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Sat Jul 13 23:42:23 2013<br>
@@ -293,7 +293,7 @@ void RAFast::spillVirtReg(MachineBasicBl<br>
// If this register is used by DBG_VALUE then insert new DBG_VALUE to<br>
// identify spilled location as the place to find corresponding variable's<br>
// value.<br>
- SmallVector<MachineInstr *, 4> &LRIDbgValues =<br>
+ SmallVectorImpl<MachineInstr *> &LRIDbgValues =<br>
LiveDbgValueMap[LRI->VirtReg];<br>
for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {<br>
MachineInstr *DBG = LRIDbgValues[li];<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jul 13 23:42:23 2013<br>
@@ -279,7 +279,7 @@ namespace {<br>
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,<br>
/// looking for aliasing nodes and adding them to the Aliases vector.<br>
void GatherAllAliases(SDNode *N, SDValue OriginalChain,<br>
- SmallVector<SDValue, 8> &Aliases);<br>
+ SmallVectorImpl<SDValue> &Aliases);<br>
<br>
/// isAlias - Return true if there is any possibility that the two addresses<br>
/// overlap.<br>
@@ -2950,7 +2950,7 @@ SDValue DAGCombiner::MatchBSwapHWordLow(<br>
/// isBSwapHWordElement - Return true if the specified node is an element<br>
/// that makes up a 32-bit packed halfword byteswap. i.e.<br>
/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)<br>
-static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {<br>
+static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {<br>
if (!N.getNode()->hasOneUse())<br>
return false;<br>
<br>
@@ -4309,7 +4309,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *<br>
// mentioned transformation is profitable.<br>
static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,<br>
unsigned ExtOpc,<br>
- SmallVector<SDNode*, 4> &ExtendNodes,<br>
+ SmallVectorImpl<SDNode *> &ExtendNodes,<br>
const TargetLowering &TLI) {<br>
bool HasCopyToRegUses = false;<br>
bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());<br>
@@ -10240,7 +10240,7 @@ bool DAGCombiner::FindAliasInfo(SDNode *<br>
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,<br>
/// looking for aliasing nodes and adding them to the Aliases vector.<br>
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,<br>
- SmallVector<SDValue, 8> &Aliases) {<br>
+ SmallVectorImpl<SDValue> &Aliases) {<br>
SmallVector<SDValue, 8> Chains; // List of chains to visit.<br>
SmallPtrSet<SDNode *, 16> Visited; // Visited node set.<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sat Jul 13 23:42:23 2013<br>
@@ -653,7 +653,7 @@ private:<br>
/// loads to load a vector with a resulting wider type. It takes<br>
/// LdChain: list of chains for the load to be generated.<br>
/// Ld: load to widen<br>
- SDValue GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,<br>
+ SDValue GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,<br>
LoadSDNode *LD);<br>
<br>
/// GenWidenVectorExtLoads - Helper function to generate a set of extension<br>
@@ -661,20 +661,20 @@ private:<br>
/// LdChain: list of chains for the load to be generated.<br>
/// Ld: load to widen<br>
/// ExtType: extension element type<br>
- SDValue GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,<br>
+ SDValue GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,<br>
LoadSDNode *LD, ISD::LoadExtType ExtType);<br>
<br>
/// Helper genWidenVectorStores - Helper function to generate a set of<br>
/// stores to store a widen vector into non widen memory<br>
/// StChain: list of chains for the stores we have generated<br>
/// ST: store of a widen value<br>
- void GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, StoreSDNode *ST);<br>
+ void GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);<br>
<br>
/// Helper genWidenVectorTruncStores - Helper function to generate a set of<br>
/// stores to store a truncate widen vector into non widen memory<br>
/// StChain: list of chains for the stores we have generated<br>
/// ST: store of a widen value<br>
- void GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,<br>
+ void GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,<br>
StoreSDNode *ST);<br>
<br>
/// Modifies a vector input (widen or narrows) to a vector of NVT. The<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sat Jul 13 23:42:23 2013<br>
@@ -2468,7 +2468,7 @@ static EVT FindMemType(SelectionDAG& DAG<br>
// LDOps: Load operators to build a vector type<br>
// [Start,End) the list of loads to use.<br>
static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,<br>
- SmallVector<SDValue, 16>& LdOps,<br>
+ SmallVectorImpl<SDValue> &LdOps,<br>
unsigned Start, unsigned End) {<br>
SDLoc dl(LdOps[Start]);<br>
EVT LdTy = LdOps[Start].getValueType();<br>
@@ -2495,7 +2495,7 @@ static SDValue BuildVectorFromScalar(Sel<br>
return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);<br>
}<br>
<br>
-SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,<br>
+SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,<br>
LoadSDNode *LD) {<br>
// The strategy assumes that we can efficiently load powers of two widths.<br>
// The routines chops the vector into the largest vector loads with the same<br>
@@ -2649,8 +2649,8 @@ SDValue DAGTypeLegalizer::GenWidenVector<br>
}<br>
<br>
SDValue<br>
-DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,<br>
- LoadSDNode * LD,<br>
+DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,<br>
+ LoadSDNode *LD,<br>
ISD::LoadExtType ExtType) {<br>
// For extension loads, it may not be more efficient to chop up the vector<br>
// and then extended it. Instead, we unroll the load and build a new vector.<br>
@@ -2697,7 +2697,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads<br>
}<br>
<br>
<br>
-void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,<br>
+void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,<br>
StoreSDNode *ST) {<br>
// The strategy assumes that we can efficiently store powers of two widths.<br>
// The routines chops the vector into the largest vector stores with the same<br>
@@ -2766,7 +2766,7 @@ void DAGTypeLegalizer::GenWidenVectorSto<br>
}<br>
<br>
void<br>
-DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,<br>
+DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,<br>
StoreSDNode *ST) {<br>
// For extension loads, it may not be more efficient to truncate the vector<br>
// and then store it. Instead, we extract each element and then store it.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Sat Jul 13 23:42:23 2013<br>
@@ -102,8 +102,8 @@ private:<br>
void InsertCopiesAndMoveSuccs(SUnit*, unsigned,<br>
const TargetRegisterClass*,<br>
const TargetRegisterClass*,<br>
- SmallVector<SUnit*, 2>&);<br>
- bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);<br>
+ SmallVectorImpl<SUnit*>&);<br>
+ bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);<br>
void ListScheduleBottomUp();<br>
<br>
/// forceUnitLatencies - The fast scheduler doesn't care about real latencies.<br>
@@ -387,7 +387,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSucce<br>
void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,<br>
const TargetRegisterClass *DestRC,<br>
const TargetRegisterClass *SrcRC,<br>
- SmallVector<SUnit*, 2> &Copies) {<br>
+ SmallVectorImpl<SUnit*> &Copies) {<br>
SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(NULL));<br>
CopyFromSU->CopySrcRC = SrcRC;<br>
CopyFromSU->CopyDstRC = DestRC;<br>
@@ -448,7 +448,7 @@ static EVT getPhysicalRegisterVT(SDNode<br>
static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,<br>
std::vector<SUnit*> &LiveRegDefs,<br>
SmallSet<unsigned, 4> &RegAdded,<br>
- SmallVector<unsigned, 4> &LRegs,<br>
+ SmallVectorImpl<unsigned> &LRegs,<br>
const TargetRegisterInfo *TRI) {<br>
bool Added = false;<br>
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {<br>
@@ -467,7 +467,7 @@ static bool CheckForLiveRegDef(SUnit *SU<br>
/// If the specific node is the last one that's available to schedule, do<br>
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.<br>
bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,<br>
- SmallVector<unsigned, 4> &LRegs){<br>
+ SmallVectorImpl<unsigned> &LRegs){<br>
if (NumLiveRegs == 0)<br>
return false;<br>
<br>
@@ -567,7 +567,7 @@ void ScheduleDAGFast::ListScheduleBottom<br>
// "expensive to copy" values to break the dependency. In case even<br>
// that doesn't work, insert cross class copies.<br>
SUnit *TrySU = NotReady[0];<br>
- SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];<br>
+ SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];<br>
assert(LRegs.size() == 1 && "Can't handle this yet!");<br>
unsigned Reg = LRegs[0];<br>
SUnit *LRDef = LiveRegDefs[Reg];<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sat Jul 13 23:42:23 2013<br>
@@ -229,8 +229,8 @@ private:<br>
void InsertCopiesAndMoveSuccs(SUnit*, unsigned,<br>
const TargetRegisterClass*,<br>
const TargetRegisterClass*,<br>
- SmallVector<SUnit*, 2>&);<br>
- bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);<br>
+ SmallVectorImpl<SUnit*>&);<br>
+ bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);<br>
<br>
void releaseInterferences(unsigned Reg = 0);<br>
<br>
@@ -1133,9 +1133,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuc<br>
/// InsertCopiesAndMoveSuccs - Insert register copies and move all<br>
/// scheduled successors of the given SUnit to the last copy.<br>
void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,<br>
- const TargetRegisterClass *DestRC,<br>
- const TargetRegisterClass *SrcRC,<br>
- SmallVector<SUnit*, 2> &Copies) {<br>
+ const TargetRegisterClass *DestRC,<br>
+ const TargetRegisterClass *SrcRC,<br>
+ SmallVectorImpl<SUnit*> &Copies) {<br>
SUnit *CopyFromSU = CreateNewSUnit(NULL);<br>
CopyFromSU->CopySrcRC = SrcRC;<br>
CopyFromSU->CopyDstRC = DestRC;<br>
@@ -1205,7 +1205,7 @@ static EVT getPhysicalRegisterVT(SDNode<br>
static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,<br>
std::vector<SUnit*> &LiveRegDefs,<br>
SmallSet<unsigned, 4> &RegAdded,<br>
- SmallVector<unsigned, 4> &LRegs,<br>
+ SmallVectorImpl<unsigned> &LRegs,<br>
const TargetRegisterInfo *TRI) {<br>
for (MCRegAliasIterator AliasI(Reg, TRI, true); AliasI.isValid(); ++AliasI) {<br>
<br>
@@ -1227,7 +1227,7 @@ static void CheckForLiveRegDef(SUnit *SU<br>
static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,<br>
std::vector<SUnit*> &LiveRegDefs,<br>
SmallSet<unsigned, 4> &RegAdded,<br>
- SmallVector<unsigned, 4> &LRegs) {<br>
+ SmallVectorImpl<unsigned> &LRegs) {<br>
// Look at all live registers. Skip Reg0 and the special CallResource.<br>
for (unsigned i = 1, e = LiveRegDefs.size()-1; i != e; ++i) {<br>
if (!LiveRegDefs[i]) continue;<br>
@@ -1252,7 +1252,7 @@ static const uint32_t *getNodeRegMask(co<br>
/// If the specific node is the last one that's available to schedule, do<br>
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.<br>
bool ScheduleDAGRRList::<br>
-DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {<br>
+DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {<br>
if (NumLiveRegs == 0)<br>
return false;<br>
<br>
@@ -1331,7 +1331,7 @@ void ScheduleDAGRRList::releaseInterfere<br>
SUnit *SU = Interferences[i-1];<br>
LRegsMapT::iterator LRegsPos = LRegsMap.find(SU);<br>
if (Reg) {<br>
- SmallVector<unsigned, 4> &LRegs = LRegsPos->second;<br>
+ SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;<br>
if (std::find(LRegs.begin(), LRegs.end(), Reg) == LRegs.end())<br>
continue;<br>
}<br>
@@ -1385,7 +1385,7 @@ SUnit *ScheduleDAGRRList::PickNodeToSche<br>
// to resolve it.<br>
for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {<br>
SUnit *TrySU = Interferences[i];<br>
- SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];<br>
+ SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];<br>
<br>
// Try unscheduling up to the point where it's safe to schedule<br>
// this node.<br>
@@ -1433,7 +1433,7 @@ SUnit *ScheduleDAGRRList::PickNodeToSche<br>
// insert cross class copies.<br>
// If it's not too expensive, i.e. cost != -1, issue copies.<br>
SUnit *TrySU = Interferences[0];<br>
- SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];<br>
+ SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];<br>
assert(LRegs.size() == 1 && "Can't handle this yet!");<br>
unsigned Reg = LRegs[0];<br>
SUnit *LRDef = LiveRegDefs[Reg];<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Sat Jul 13 23:42:23 2013<br>
@@ -700,11 +700,10 @@ namespace {<br>
}<br>
<br>
/// ProcessSDDbgValues - Process SDDbgValues associated with this node.<br>
-static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG,<br>
- InstrEmitter &Emitter,<br>
- SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,<br>
- DenseMap<SDValue, unsigned> &VRBaseMap,<br>
- unsigned Order) {<br>
+static void<br>
+ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,<br>
+ SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,<br>
+ DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {<br>
if (!N->getHasDebugValue())<br>
return;<br>
<br>
@@ -731,11 +730,11 @@ static void ProcessSDDbgValues(SDNode *N<br>
// ProcessSourceNode - Process nodes with source order numbers. These are added<br>
// to a vector which EmitSchedule uses to determine how to insert dbg_value<br>
// instructions in the right order.<br>
-static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,<br>
- InstrEmitter &Emitter,<br>
- DenseMap<SDValue, unsigned> &VRBaseMap,<br>
- SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,<br>
- SmallSet<unsigned, 8> &Seen) {<br>
+static void<br>
+ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,<br>
+ DenseMap<SDValue, unsigned> &VRBaseMap,<br>
+ SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,<br>
+ SmallSet<unsigned, 8> &Seen) {<br>
unsigned Order = N->getIROrder();<br>
if (!Order || !Seen.insert(Order)) {<br>
// Process any valid SDDbgValues even if node does not have any order<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jul 13 23:42:23 2013<br>
@@ -6077,9 +6077,10 @@ bool SDNode::hasPredecessor(const SDNode<br>
return hasPredecessorHelper(N, Visited, Worklist);<br>
}<br>
<br>
-bool SDNode::hasPredecessorHelper(const SDNode *N,<br>
- SmallPtrSet<const SDNode *, 32> &Visited,<br>
- SmallVector<const SDNode *, 16> &Worklist) const {<br>
+bool<br>
+SDNode::hasPredecessorHelper(const SDNode *N,<br>
+ SmallPtrSet<const SDNode *, 32> &Visited,<br>
+ SmallVectorImpl<const SDNode *> &Worklist) const {<br>
if (Visited.empty()) {<br>
Worklist.push_back(this);<br>
} else {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp Sat Jul 13 23:42:23 2013<br>
@@ -554,7 +554,7 @@ bool PEI::calculateSets(MachineFunction<br>
/// _outside_ the computed minimal placement regions have been covered.<br>
///<br>
bool PEI::addUsesForMEMERegion(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4>& blks) {<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks) {<br>
if (MBB->succ_size() < 2 && MBB->pred_size() < 2) {<br>
bool processThisBlock = false;<br>
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),<br>
@@ -629,7 +629,7 @@ bool PEI::addUsesForMEMERegion(MachineBa<br>
/// addUsesForTopLevelLoops - add uses for CSRs used inside top<br>
/// level loops to the exit blocks of those loops.<br>
///<br>
-bool PEI::addUsesForTopLevelLoops(SmallVector<MachineBasicBlock*, 4>& blks) {<br>
+bool PEI::addUsesForTopLevelLoops(SmallVectorImpl<MachineBasicBlock *> &blks) {<br>
bool addedUses = false;<br>
<br>
// Place restores for top level loops where needed.<br>
@@ -674,7 +674,7 @@ bool PEI::addUsesForTopLevelLoops(SmallV<br>
/// multi-entry/exit regions.<br>
///<br>
bool PEI::calcSpillPlacements(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4> &blks,<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks,<br>
CSRegBlockMap &prevSpills) {<br>
bool placedSpills = false;<br>
// Intersect (CSRegs - AnticIn[P]) for P in Predecessors(MBB)<br>
@@ -736,7 +736,7 @@ bool PEI::calcSpillPlacements(MachineBas<br>
/// multi-entry/exit regions.<br>
///<br>
bool PEI::calcRestorePlacements(MachineBasicBlock* MBB,<br>
- SmallVector<MachineBasicBlock*, 4> &blks,<br>
+ SmallVectorImpl<MachineBasicBlock *> &blks,<br>
CSRegBlockMap &prevRestores) {<br>
bool placedRestores = false;<br>
// Intersect (CSRegs - AvailOut[S]) for S in Successors(MBB)<br>
<br>
Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Sat Jul 13 23:42:23 2013<br>
@@ -106,7 +106,7 @@ namespace {<br>
bool OverlapWithAssignments(LiveInterval *li, int Color) const;<br>
int ColorSlot(LiveInterval *li);<br>
bool ColorSlots(MachineFunction &MF);<br>
- void RewriteInstruction(MachineInstr *MI, SmallVector<int, 16> &SlotMapping,<br>
+ void RewriteInstruction(MachineInstr *MI, SmallVectorImpl<int> &SlotMapping,<br>
MachineFunction &MF);<br>
bool RemoveDeadStores(MachineBasicBlock* MBB);<br>
};<br>
@@ -340,7 +340,7 @@ bool StackSlotColoring::ColorSlots(Machi<br>
/// RewriteInstruction - Rewrite specified instruction by replacing references<br>
/// to old frame index with new one.<br>
void StackSlotColoring::RewriteInstruction(MachineInstr *MI,<br>
- SmallVector<int, 16> &SlotMapping,<br>
+ SmallVectorImpl<int> &SlotMapping,<br>
MachineFunction &MF) {<br>
// Update the operands.<br>
for (unsigned i = 0, ee = MI->getNumOperands(); i != ee; ++i) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Sat Jul 13 23:42:23 2013<br>
@@ -86,7 +86,7 @@ namespace {<br>
void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,<br>
MachineBasicBlock *PredBB,<br>
DenseMap<unsigned, unsigned> &LocalVRMap,<br>
- SmallVector<std::pair<unsigned,unsigned>, 4> &Copies,<br>
+ SmallVectorImpl<std::pair<unsigned,unsigned> > &Copies,<br>
const DenseSet<unsigned> &UsedByPhi,<br>
bool Remove);<br>
void DuplicateInstruction(MachineInstr *MI,<br>
@@ -96,7 +96,7 @@ namespace {<br>
DenseMap<unsigned, unsigned> &LocalVRMap,<br>
const DenseSet<unsigned> &UsedByPhi);<br>
void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
SmallSetVector<MachineBasicBlock*, 8> &Succs);<br>
bool TailDuplicateBlocks(MachineFunction &MF);<br>
bool shouldTailDuplicate(const MachineFunction &MF,<br>
@@ -104,14 +104,14 @@ namespace {<br>
bool isSimpleBB(MachineBasicBlock *TailBB);<br>
bool canCompletelyDuplicateBB(MachineBasicBlock &BB);<br>
bool duplicateSimpleBB(MachineBasicBlock *TailBB,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
const DenseSet<unsigned> &RegsUsedByPhi,<br>
- SmallVector<MachineInstr*, 16> &Copies);<br>
+ SmallVectorImpl<MachineInstr *> &Copies);<br>
bool TailDuplicate(MachineBasicBlock *TailBB,<br>
bool IsSimple,<br>
MachineFunction &MF,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
- SmallVector<MachineInstr*, 16> &Copies);<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
+ SmallVectorImpl<MachineInstr *> &Copies);<br>
bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,<br>
bool IsSimple,<br>
MachineFunction &MF);<br>
@@ -386,7 +386,7 @@ void TailDuplicatePass::ProcessPHI(Machi<br>
MachineBasicBlock *TailBB,<br>
MachineBasicBlock *PredBB,<br>
DenseMap<unsigned, unsigned> &LocalVRMap,<br>
- SmallVector<std::pair<unsigned,unsigned>, 4> &Copies,<br>
+ SmallVectorImpl<std::pair<unsigned,unsigned>> &Copies,<br>
const DenseSet<unsigned> &RegsUsedByPhi,<br>
bool Remove) {<br>
unsigned DefReg = MI->getOperand(0).getReg();<br>
@@ -452,7 +452,7 @@ void TailDuplicatePass::DuplicateInstruc<br>
/// instructions in them accordingly.<br>
void<br>
TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
SmallSetVector<MachineBasicBlock*,8> &Succs) {<br>
for (SmallSetVector<MachineBasicBlock*, 8>::iterator SI = Succs.begin(),<br>
SE = Succs.end(); SI != SE; ++SI) {<br>
@@ -662,9 +662,9 @@ TailDuplicatePass::canCompletelyDuplicat<br>
<br>
bool<br>
TailDuplicatePass::duplicateSimpleBB(MachineBasicBlock *TailBB,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
- const DenseSet<unsigned> &UsedByPhi,<br>
- SmallVector<MachineInstr*, 16> &Copies) {<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
+ const DenseSet<unsigned> &UsedByPhi,<br>
+ SmallVectorImpl<MachineInstr *> &Copies) {<br>
SmallPtrSet<MachineBasicBlock*, 8> Succs(TailBB->succ_begin(),<br>
TailBB->succ_end());<br>
SmallVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),<br>
@@ -742,8 +742,8 @@ bool<br>
TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,<br>
bool IsSimple,<br>
MachineFunction &MF,<br>
- SmallVector<MachineBasicBlock*, 8> &TDBBs,<br>
- SmallVector<MachineInstr*, 16> &Copies) {<br>
+ SmallVectorImpl<MachineBasicBlock *> &TDBBs,<br>
+ SmallVectorImpl<MachineInstr *> &Copies) {<br>
DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');<br>
<br>
DenseSet<unsigned> UsedByPhi;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1539,7 +1539,7 @@ bool TwoAddressInstructionPass::runOnMac<br>
// transformations that may either eliminate the tied operands or<br>
// improve the opportunities for coalescing away the register copy.<br>
if (TiedOperands.size() == 1) {<br>
- SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs<br>
+ SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs<br>
= TiedOperands.begin()->second;<br>
if (TiedPairs.size() == 1) {<br>
unsigned SrcIdx = TiedPairs[0].first;<br>
<br>
Modified: llvm/trunk/lib/IR/Metadata.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Metadata.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Metadata.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/Metadata.cpp (original)<br>
+++ llvm/trunk/lib/IR/Metadata.cpp Sat Jul 13 23:42:23 2013<br>
@@ -422,7 +422,7 @@ static bool canBeMerged(const ConstantRa<br>
return !A.intersectWith(B).isEmptySet() || isContiguous(A, B);<br>
}<br>
<br>
-static bool tryMergeRange(SmallVector<Value*, 4> &EndPoints, ConstantInt *Low,<br>
+static bool tryMergeRange(SmallVectorImpl<Value *> &EndPoints, ConstantInt *Low,<br>
ConstantInt *High) {<br>
ConstantRange NewRange(Low->getValue(), High->getValue());<br>
unsigned Size = EndPoints.size();<br>
@@ -439,7 +439,7 @@ static bool tryMergeRange(SmallVector<Va<br>
return false;<br>
}<br>
<br>
-static void addRange(SmallVector<Value*, 4> &EndPoints, ConstantInt *Low,<br>
+static void addRange(SmallVectorImpl<Value *> &EndPoints, ConstantInt *Low,<br>
ConstantInt *High) {<br>
if (!EndPoints.empty())<br>
if (tryMergeRange(EndPoints, Low, High))<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1079,9 +1079,9 @@ AArch64TargetLowering::LowerCall(CallLow<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &IsTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -74,7 +74,7 @@ namespace {<br>
class ARMCCState : public CCState {<br>
public:<br>
ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,<br>
- const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,<br>
+ const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,<br>
LLVMContext &C, ParmContext PC)<br>
: CCState(CC, isVarArg, MF, TM, locs, C) {<br>
assert(((PC == Call) || (PC == Prologue)) &&<br>
@@ -1330,7 +1330,7 @@ void ARMTargetLowering::PassF64ArgInRegs<br>
RegsToPassVector &RegsToPass,<br>
CCValAssign &VA, CCValAssign &NextVA,<br>
SDValue &StackPtr,<br>
- SmallVector<SDValue, 8> &MemOpChains,<br>
+ SmallVectorImpl<SDValue> &MemOpChains,<br>
ISD::ArgFlagsTy Flags) const {<br>
<br>
SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,<br>
@@ -1358,9 +1358,9 @@ ARMTargetLowering::LowerCall(TargetLower<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sat Jul 13 23:42:23 2013<br>
@@ -417,7 +417,7 @@ namespace llvm {<br>
RegsToPassVector &RegsToPass,<br>
CCValAssign &VA, CCValAssign &NextVA,<br>
SDValue &StackPtr,<br>
- SmallVector<SDValue, 8> &MemOpChains,<br>
+ SmallVectorImpl<SDValue> &MemOpChains,<br>
ISD::ArgFlagsTy Flags) const;<br>
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,<br>
SDValue &Root, SelectionDAG &DAG,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sat Jul 13 23:42:23 2013<br>
@@ -109,12 +109,12 @@ namespace {<br>
unsigned PredReg,<br>
unsigned Scratch,<br>
DebugLoc dl,<br>
- SmallVector<MachineBasicBlock::iterator, 4> &Merges);<br>
+ SmallVectorImpl<MachineBasicBlock::iterator> &Merges);<br>
void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,<br>
int Opcode, unsigned Size,<br>
ARMCC::CondCodes Pred, unsigned PredReg,<br>
unsigned Scratch, MemOpQueue &MemOps,<br>
- SmallVector<MachineBasicBlock::iterator, 4> &Merges);<br>
+ SmallVectorImpl<MachineBasicBlock::iterator> &Merges);<br>
<br>
void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);<br>
bool FixInvalidRegPairOp(MachineBasicBlock &MBB,<br>
@@ -371,7 +371,7 @@ void ARMLoadStoreOpt::MergeOpsUpdate(Mac<br>
ARMCC::CondCodes Pred, unsigned PredReg,<br>
unsigned Scratch,<br>
DebugLoc dl,<br>
- SmallVector<MachineBasicBlock::iterator, 4> &Merges) {<br>
+ SmallVectorImpl<MachineBasicBlock::iterator> &Merges) {<br>
// First calculate which of the registers should be killed by the merged<br>
// instruction.<br>
const unsigned insertPos = memOps[insertAfter].Position;<br>
@@ -444,10 +444,10 @@ void ARMLoadStoreOpt::MergeOpsUpdate(Mac<br>
/// load / store multiple instructions.<br>
void<br>
ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,<br>
- unsigned Base, int Opcode, unsigned Size,<br>
- ARMCC::CondCodes Pred, unsigned PredReg,<br>
- unsigned Scratch, MemOpQueue &MemOps,<br>
- SmallVector<MachineBasicBlock::iterator, 4> &Merges) {<br>
+ unsigned Base, int Opcode, unsigned Size,<br>
+ ARMCC::CondCodes Pred, unsigned PredReg,<br>
+ unsigned Scratch, MemOpQueue &MemOps,<br>
+ SmallVectorImpl<MachineBasicBlock::iterator> &Merges) {<br>
bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);<br>
int Offset = MemOps[SIndex].Offset;<br>
int SOffset = Offset;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.cpp Sat Jul 13 23:42:23 2013<br>
@@ -25,7 +25,7 @@ using namespace llvm;<br>
<br>
Hexagon_CCState::Hexagon_CCState(CallingConv::ID CC, bool isVarArg,<br>
const TargetMachine &tm,<br>
- SmallVector<CCValAssign, 16> &locs,<br>
+ SmallVectorImpl<CCValAssign> &locs,<br>
LLVMContext &c)<br>
: CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) {<br>
// No stack is used.<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonCallingConvLower.h Sat Jul 13 23:42:23 2013<br>
@@ -48,14 +48,14 @@ class Hexagon_CCState {<br>
CallingConv::ID CallingConv;<br>
bool IsVarArg;<br>
const TargetMachine &TM;<br>
- SmallVector<CCValAssign, 16> &Locs;<br>
+ SmallVectorImpl<CCValAssign> &Locs;<br>
LLVMContext &Context;<br>
<br>
unsigned StackOffset;<br>
SmallVector<uint32_t, 16> UsedRegs;<br>
public:<br>
Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,<br>
- SmallVector<CCValAssign, 16> &locs, LLVMContext &c);<br>
+ SmallVectorImpl<CCValAssign> &locs, LLVMContext &c);<br>
<br>
void addLoc(const CCValAssign &V) {<br>
Locs.push_back(V);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Sat Jul 13 23:42:23 2013<br>
@@ -134,7 +134,7 @@ namespace {<br>
/// has a computable trip count and, if so, return a value that represents<br>
/// the trip count expression.<br>
CountValue *getLoopTripCount(MachineLoop *L,<br>
- SmallVector<MachineInstr*, 2> &OldInsts);<br>
+ SmallVectorImpl<MachineInstr *> &OldInsts);<br>
<br>
/// \brief Return the expression that represents the number of times<br>
/// a loop iterates. The function takes the operands that represent the<br>
@@ -164,7 +164,7 @@ namespace {<br>
<br>
/// \brief Return true if the instruction is now dead.<br>
bool isDead(const MachineInstr *MI,<br>
- SmallVector<MachineInstr*, 1> &DeadPhis) const;<br>
+ SmallVectorImpl<MachineInstr *> &DeadPhis) const;<br>
<br>
/// \brief Remove the instruction if it is now dead.<br>
void removeIfDead(MachineInstr *MI);<br>
@@ -428,7 +428,7 @@ bool HexagonHardwareLoops::findInduction<br>
/// induction variable patterns that are used in the calculation for<br>
/// the number of time the loop is executed.<br>
CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,<br>
- SmallVector<MachineInstr*, 2> &OldInsts) {<br>
+ SmallVectorImpl<MachineInstr *> &OldInsts) {<br>
MachineBasicBlock *TopMBB = L->getTopBlock();<br>
MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();<br>
assert(PI != TopMBB->pred_end() &&<br>
@@ -890,7 +890,7 @@ bool HexagonHardwareLoops::containsInval<br>
/// for inline asm, physical registers and instructions with side effects<br>
/// removed.<br>
bool HexagonHardwareLoops::isDead(const MachineInstr *MI,<br>
- SmallVector<MachineInstr*, 1> &DeadPhis) const {<br>
+ SmallVectorImpl<MachineInstr *> &DeadPhis) const {<br>
// Examine each operand.<br>
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br>
const MachineOperand &MO = MI->getOperand(i);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -382,10 +382,10 @@ SDValue<br>
HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
- SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SDLoc &dl = CLI.DL;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -38,8 +38,8 @@ static cl::opt<bool> MBDisableStackAdjus<br>
cl::desc("Disable MBlaze stack layout adjustment."),<br>
cl::Hidden);<br>
<br>
-static void replaceFrameIndexes(MachineFunction &MF,<br>
- SmallVector<std::pair<int,int64_t>, 16> &FR) {<br>
+static void replaceFrameIndexes(MachineFunction &MF,<br>
+ SmallVectorImpl<std::pair<int,int64_t> > &FR) {<br>
MachineFrameInfo *MFI = MF.getFrameInfo();<br>
MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();<br>
const SmallVectorImpl<std::pair<int,int64_t> >::iterator FRB = FR.begin();<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -687,9 +687,9 @@ LowerCall(TargetLowering::CallLoweringIn<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h Sat Jul 13 23:42:23 2013<br>
@@ -118,7 +118,7 @@ public:<br>
return false;<br>
}<br>
<br>
- const SmallVector<int, 16>& getLiveIn() const { return LiveInFI; }<br>
+ const SmallVectorImpl<int> &getLiveIn() const { return LiveInFI; }<br>
<br>
void recordReplacement(int OFI, int NFI) {<br>
FIReplacements.insert(std::make_pair(OFI,NFI));<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -279,9 +279,9 @@ MSP430TargetLowering::LowerCall(TargetLo<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -2323,9 +2323,9 @@ MipsTargetLowering::LowerCall(TargetLowe<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc DL = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &IsTailCall = CLI.IsTailCall;<br>
@@ -3383,7 +3383,7 @@ copyByValRegs(SDValue Chain, SDLoc DL, s<br>
void MipsTargetLowering::<br>
passByValArg(SDValue Chain, SDLoc DL,<br>
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,<br>
- SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,<br>
+ SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,<br>
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,<br>
const MipsCC &CC, const ByValArgInfo &ByVal,<br>
const ISD::ArgFlagsTy &Flags, bool isLittle) const {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Sat Jul 13 23:42:23 2013<br>
@@ -386,7 +386,7 @@ namespace llvm {<br>
/// passByValArg - Pass a byval argument in registers or on stack.<br>
void passByValArg(SDValue Chain, SDLoc DL,<br>
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,<br>
- SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,<br>
+ SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,<br>
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,<br>
const MipsCC &CC, const ByValArgInfo &ByVal,<br>
const ISD::ArgFlagsTy &Flags, bool isLittle) const;<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -493,9 +493,9 @@ SDValue NVPTXTargetLowering::LowerCall(T<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -369,7 +369,7 @@ void PPCFrameLowering::emitPrologue(Mach<br>
// Check if the link register (LR) must be saved.<br>
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();<br>
bool MustSaveLR = FI->mustSaveLR();<br>
- const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();<br>
+ const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();<br>
// Do we have a frame pointer for this function?<br>
bool HasFP = hasFP(MF);<br>
<br>
@@ -642,7 +642,7 @@ void PPCFrameLowering::emitEpilogue(Mach<br>
// Check if the link register (LR) has been saved.<br>
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();<br>
bool MustSaveLR = FI->mustSaveLR();<br>
- const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();<br>
+ const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();<br>
// Do we have a frame pointer for this function?<br>
bool HasFP = hasFP(MF);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -2957,8 +2957,8 @@ struct TailCallArgumentInfo {<br>
static void<br>
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,<br>
SDValue Chain,<br>
- const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,<br>
- SmallVector<SDValue, 8> &MemOpChains,<br>
+ const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,<br>
+ SmallVectorImpl<SDValue> &MemOpChains,<br>
SDLoc dl) {<br>
for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {<br>
SDValue Arg = TailCallArgs[i].Arg;<br>
@@ -3016,7 +3016,7 @@ static SDValue EmitTailCallStoreFPAndRet<br>
static void<br>
CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,<br>
SDValue Arg, int SPDiff, unsigned ArgOffset,<br>
- SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {<br>
+ SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {<br>
int Offset = ArgOffset + SPDiff;<br>
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;<br>
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);<br>
@@ -3081,8 +3081,8 @@ static void<br>
LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,<br>
SDValue Arg, SDValue PtrOff, int SPDiff,<br>
unsigned ArgOffset, bool isPPC64, bool isTailCall,<br>
- bool isVector, SmallVector<SDValue, 8> &MemOpChains,<br>
- SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,<br>
+ bool isVector, SmallVectorImpl<SDValue> &MemOpChains,<br>
+ SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,<br>
SDLoc dl) {<br>
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();<br>
if (!isTailCall) {<br>
@@ -3106,7 +3106,7 @@ static<br>
void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,<br>
SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,<br>
SDValue LROp, SDValue FPOp, bool isDarwinABI,<br>
- SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {<br>
+ SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
<br>
// Emit a sequence of copyto/copyfrom virtual registers for arguments that<br>
@@ -3133,8 +3133,8 @@ void PrepareTailCall(SelectionDAG &DAG,<br>
static<br>
unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,<br>
SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,<br>
- SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,<br>
- SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,<br>
+ SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,<br>
+ SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,<br>
const PPCSubtarget &PPCSubTarget) {<br>
<br>
bool isPPC64 = PPCSubTarget.isPPC64();<br>
@@ -3460,10 +3460,10 @@ SDValue<br>
PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
- SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SDLoc &dl = CLI.DL;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Sat Jul 13 23:42:23 2013<br>
@@ -160,7 +160,7 @@ public:<br>
int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }<br>
void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }<br>
<br>
- const SmallVector<unsigned, 3> &<br>
+ const SmallVectorImpl<unsigned> &<br>
getMustSaveCRs() const { return MustSaveCRs; }<br>
void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }<br>
};<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp Sat Jul 13 23:42:23 2013<br>
@@ -92,7 +92,7 @@ void PrintLoopinfo(const LoopinfoT &Loop<br>
}<br>
<br>
template<class NodeT><br>
-void ReverseVector(SmallVector<NodeT *, DEFAULT_VEC_SLOTS> &Src) {<br>
+void ReverseVector(SmallVectorImpl<NodeT *> &Src) {<br>
size_t sz = Src.size();<br>
for (size_t i = 0; i < sz/2; ++i) {<br>
NodeT *t = Src[i];<br>
@@ -258,7 +258,7 @@ private:<br>
BlockT *normalizeInfiniteLoopExit(LoopT *LoopRep);<br>
void removeUnconditionalBranch(BlockT *SrcBlock);<br>
void removeRedundantConditionalBranch(BlockT *SrcBlock);<br>
- void addDummyExitBlock(SmallVector<BlockT *, DEFAULT_VEC_SLOTS> &RetBlocks);<br>
+ void addDummyExitBlock(SmallVectorImpl<BlockT *> &RetBlocks);<br>
<br>
void removeSuccessor(BlockT *SrcBlock);<br>
BlockT *cloneBlockForPredecessor(BlockT *CurBlock, BlockT *PredBlock);<br>
@@ -2076,8 +2076,8 @@ void CFGStructurizer<PassT>::removeRedun<br>
} //removeRedundantConditionalBranch<br>
<br>
template<class PassT><br>
-void CFGStructurizer<PassT>::addDummyExitBlock(SmallVector<BlockT*,<br>
- DEFAULT_VEC_SLOTS> &retBlks) {<br>
+void CFGStructurizer<PassT>::addDummyExitBlock(SmallVectorImpl<BlockT *><br>
+ &retBlks) {<br>
BlockT *dummyExitBlk = funcRep->CreateMachineBasicBlock();<br>
funcRep->push_back(dummyExitBlk); //insert to function<br>
CFGTraits::insertInstrEnd(dummyExitBlk, AMDGPU::RETURN, passRep);<br>
<br>
Modified: llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/R600EmitClauseMarkers.cpp Sat Jul 13 23:42:23 2013<br>
@@ -107,7 +107,7 @@ private:<br>
bool SubstituteKCacheBank(MachineInstr *MI,<br>
std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {<br>
std::vector<std::pair<unsigned, unsigned> > UsedKCache;<br>
- const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Consts =<br>
+ const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Consts =<br>
TII->getSrcs(MI);<br>
assert((TII->isALUInstr(MI->getOpcode()) ||<br>
MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");<br>
<br>
Modified: llvm/trunk/lib/Target/R600/R600InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600InstrInfo.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600InstrInfo.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/R600InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/R600InstrInfo.cpp Sat Jul 13 23:42:23 2013<br>
@@ -519,7 +519,7 @@ R600InstrInfo::fitsConstReadLimitations(<br>
if (!isALUInstr(MI->getOpcode()))<br>
continue;<br>
<br>
- const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Srcs =<br>
+ const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =<br>
getSrcs(MI);<br>
<br>
for (unsigned j = 0, e = Srcs.size(); j < e; j++) {<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -654,9 +654,9 @@ SparcTargetLowering::LowerCall_32(Target<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -679,9 +679,9 @@ SystemZTargetLowering::LowerCall(CallLow<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
SDLoc &DL = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -2280,10 +2280,10 @@ SDValue<br>
X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
- SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SDLoc &dl = CLI.DL;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
CallingConv::ID CallConv = CLI.CallConv;<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Sat Jul 13 23:42:23 2013<br>
@@ -847,10 +847,10 @@ SDValue<br>
XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
SelectionDAG &DAG = CLI.DAG;<br>
- SDLoc &dl = CLI.DL;<br>
- SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;<br>
- SmallVector<SDValue, 32> &OutVals = CLI.OutVals;<br>
- SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;<br>
+ SDLoc &dl = CLI.DL;<br>
+ SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;<br>
+ SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;<br>
+ SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;<br>
SDValue Chain = CLI.Chain;<br>
SDValue Callee = CLI.Callee;<br>
bool &isTailCall = CLI.IsTailCall;<br>
<br>
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1299,7 +1299,7 @@ Instruction *InstCombiner::visitAnd(Bina<br>
/// always in the local (OverallLeftShift) coordinate space.<br>
///<br>
static bool CollectBSwapParts(Value *V, int OverallLeftShift, uint32_t ByteMask,<br>
- SmallVector<Value*, 8> &ByteValues) {<br>
+ SmallVectorImpl<Value *> &ByteValues) {<br>
if (Instruction *I = dyn_cast<Instruction>(V)) {<br>
// If this is an or instruction, it may be an inner node of the bswap.<br>
if (I->getOpcode() == Instruction::Or) {<br>
<br>
Modified: llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/ObjCARC/ObjCARCOpts.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1198,9 +1198,9 @@ namespace {<br>
MapVector<Value *, RRInfo> &Retains,<br>
DenseMap<Value *, RRInfo> &Releases,<br>
Module *M,<br>
- SmallVector<Instruction *, 4> &NewRetains,<br>
- SmallVector<Instruction *, 4> &NewReleases,<br>
- SmallVector<Instruction *, 8> &DeadInsts,<br>
+ SmallVectorImpl<Instruction *> &NewRetains,<br>
+ SmallVectorImpl<Instruction *> &NewReleases,<br>
+ SmallVectorImpl<Instruction *> &DeadInsts,<br>
RRInfo &RetainsToMove,<br>
RRInfo &ReleasesToMove,<br>
Value *Arg,<br>
@@ -2477,9 +2477,9 @@ ObjCARCOpt::ConnectTDBUTraversals(DenseM<br>
MapVector<Value *, RRInfo> &Retains,<br>
DenseMap<Value *, RRInfo> &Releases,<br>
Module *M,<br>
- SmallVector<Instruction *, 4> &NewRetains,<br>
- SmallVector<Instruction *, 4> &NewReleases,<br>
- SmallVector<Instruction *, 8> &DeadInsts,<br>
+ SmallVectorImpl<Instruction *> &NewRetains,<br>
+ SmallVectorImpl<Instruction *> &NewReleases,<br>
+ SmallVectorImpl<Instruction *> &DeadInsts,<br>
RRInfo &RetainsToMove,<br>
RRInfo &ReleasesToMove,<br>
Value *Arg,<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Sat Jul 13 23:42:23 2013<br>
@@ -51,8 +51,8 @@ namespace {<br>
}<br>
<br>
private:<br>
- bool isLoopDead(Loop *L, SmallVector<BasicBlock*, 4> &exitingBlocks,<br>
- SmallVector<BasicBlock*, 4> &exitBlocks,<br>
+ bool isLoopDead(Loop *L, SmallVectorImpl<BasicBlock *> &exitingBlocks,<br>
+ SmallVectorImpl<BasicBlock *> &exitBlocks,<br>
bool &Changed, BasicBlock *Preheader);<br>
<br>
};<br>
@@ -77,8 +77,8 @@ Pass *llvm::createLoopDeletionPass() {<br>
/// checked for unique exit and exiting blocks, and that the code is in LCSSA<br>
/// form.<br>
bool LoopDeletion::isLoopDead(Loop *L,<br>
- SmallVector<BasicBlock*, 4> &exitingBlocks,<br>
- SmallVector<BasicBlock*, 4> &exitBlocks,<br>
+ SmallVectorImpl<BasicBlock *> &exitingBlocks,<br>
+ SmallVectorImpl<BasicBlock *> &exitBlocks,<br>
bool &Changed, BasicBlock *Preheader) {<br>
BasicBlock *exitBlock = exitBlocks[0];<br>
<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Sat Jul 13 23:42:23 2013<br>
@@ -196,7 +196,7 @@ namespace {<br>
<br>
/// Split all of the edges from inside the loop to their exit blocks.<br>
/// Update the appropriate Phi nodes as we do so.<br>
- void SplitExitEdges(Loop *L, const SmallVector<BasicBlock *, 8> &ExitBlocks);<br>
+ void SplitExitEdges(Loop *L, const SmallVectorImpl<BasicBlock *> &ExitBlocks);<br>
<br>
bool UnswitchIfProfitable(Value *LoopCond, Constant *Val);<br>
void UnswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,<br>
@@ -752,7 +752,7 @@ void LoopUnswitch::UnswitchTrivialCondit<br>
/// SplitExitEdges - Split all of the edges from inside the loop to their exit<br>
/// blocks. Update the appropriate Phi nodes as we do so.<br>
void LoopUnswitch::SplitExitEdges(Loop *L,<br>
- const SmallVector<BasicBlock *, 8> &ExitBlocks){<br>
+ const SmallVectorImpl<BasicBlock *> &ExitBlocks){<br>
<br>
for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {<br>
BasicBlock *ExitBlock = ExitBlocks[i];<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Sat Jul 13 23:42:23 2013<br>
@@ -439,7 +439,7 @@ private:<br>
// getFeasibleSuccessors - Return a vector of booleans to indicate which<br>
// successors are reachable from a given terminator instruction.<br>
//<br>
- void getFeasibleSuccessors(TerminatorInst &TI, SmallVector<bool, 16> &Succs);<br>
+ void getFeasibleSuccessors(TerminatorInst &TI, SmallVectorImpl<bool> &Succs);<br>
<br>
// isEdgeFeasible - Return true if the control flow edge from the 'From' basic<br>
// block to the 'To' basic block is currently feasible.<br>
@@ -513,7 +513,7 @@ private:<br>
// successors are reachable from a given terminator instruction.<br>
//<br>
void SCCPSolver::getFeasibleSuccessors(TerminatorInst &TI,<br>
- SmallVector<bool, 16> &Succs) {<br>
+ SmallVectorImpl<bool> &Succs) {<br>
Succs.resize(TI.getNumSuccessors());<br>
if (BranchInst *BI = dyn_cast<BranchInst>(&TI)) {<br>
if (BI->isUnconditional()) {<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Sat Jul 13 23:42:23 2013<br>
@@ -166,21 +166,21 @@ namespace {<br>
void DeleteDeadInstructions();<br>
<br>
void RewriteForScalarRepl(Instruction *I, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteBitCast(BitCastInst *BC, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteGEP(GetElementPtrInst *GEPI, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI,<br>
uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst,<br>
AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteStoreUserOfWholeAlloca(StoreInst *SI, AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts);<br>
+ SmallVectorImpl<AllocaInst *> &NewElts);<br>
bool ShouldAttemptScalarRepl(AllocaInst *AI);<br>
};<br>
<br>
@@ -1865,7 +1865,7 @@ bool SROA::TypeHasComponent(Type *T, uin<br>
/// Offset indicates the position within AI that is referenced by this<br>
/// instruction.<br>
void SROA::RewriteForScalarRepl(Instruction *I, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI!=E;) {<br>
Use &TheUse = UI.getUse();<br>
Instruction *User = cast<Instruction>(*UI++);<br>
@@ -1979,7 +1979,7 @@ void SROA::RewriteForScalarRepl(Instruct<br>
/// RewriteBitCast - Update a bitcast reference to the alloca being replaced<br>
/// and recursively continue updating all of its uses.<br>
void SROA::RewriteBitCast(BitCastInst *BC, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
RewriteForScalarRepl(BC, AI, Offset, NewElts);<br>
if (BC->getOperand(0) != AI)<br>
return;<br>
@@ -2037,7 +2037,7 @@ uint64_t SROA::FindElementAndOffset(Type<br>
/// elements of the alloca that are being split apart, and if so, rewrite<br>
/// the GEP to be relative to the new element.<br>
void SROA::RewriteGEP(GetElementPtrInst *GEPI, AllocaInst *AI, uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
uint64_t OldOffset = Offset;<br>
SmallVector<Value*, 8> Indices(GEPI->op_begin() + 1, GEPI->op_end());<br>
// If the GEP was dynamic then it must have been a dynamic vector lookup.<br>
@@ -2099,7 +2099,7 @@ void SROA::RewriteGEP(GetElementPtrInst<br>
/// to mark the lifetime of the scalarized memory.<br>
void SROA::RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI,<br>
uint64_t Offset,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
ConstantInt *OldSize = cast<ConstantInt>(II->getArgOperand(0));<br>
// Put matching lifetime markers on everything from Offset up to<br>
// Offset+OldSize.<br>
@@ -2153,9 +2153,10 @@ void SROA::RewriteLifetimeIntrinsic(Intr<br>
<br>
/// RewriteMemIntrinUserOfAlloca - MI is a memcpy/memset/memmove from or to AI.<br>
/// Rewrite it to copy or set the elements of the scalarized memory.<br>
-void SROA::RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst,<br>
- AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+void<br>
+SROA::RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst,<br>
+ AllocaInst *AI,<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
// If this is a memcpy/memmove, construct the other pointer as the<br>
// appropriate type. The "Other" pointer is the pointer that goes to memory<br>
// that doesn't have anything to do with the alloca that we are promoting. For<br>
@@ -2326,8 +2327,9 @@ void SROA::RewriteMemIntrinUserOfAlloca(<br>
/// RewriteStoreUserOfWholeAlloca - We found a store of an integer that<br>
/// overwrites the entire allocation. Extract out the pieces of the stored<br>
/// integer and store them individually.<br>
-void SROA::RewriteStoreUserOfWholeAlloca(StoreInst *SI, AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts){<br>
+void<br>
+SROA::RewriteStoreUserOfWholeAlloca(StoreInst *SI, AllocaInst *AI,<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
// Extract each element out of the integer according to its structure offset<br>
// and store the element value to the individual alloca.<br>
Value *SrcVal = SI->getOperand(0);<br>
@@ -2440,8 +2442,9 @@ void SROA::RewriteStoreUserOfWholeAlloca<br>
<br>
/// RewriteLoadUserOfWholeAlloca - We found a load of the entire allocation to<br>
/// an integer. Load the individual pieces to form the aggregate value.<br>
-void SROA::RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocaInst *AI,<br>
- SmallVector<AllocaInst*, 32> &NewElts) {<br>
+void<br>
+SROA::RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocaInst *AI,<br>
+ SmallVectorImpl<AllocaInst *> &NewElts) {<br>
// Extract each element out of the NewElts according to its structure offset<br>
// and form the result value.<br>
Type *AllocaEltTy = AI->getAllocatedType();<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Sat Jul 13 23:42:23 2013<br>
@@ -99,16 +99,16 @@ namespace {<br>
bool EliminateRecursiveTailCall(CallInst *CI, ReturnInst *Ret,<br>
BasicBlock *&OldEntry,<br>
bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
bool CannotTailCallElimCallsMarkedTail);<br>
bool FoldReturnAndProcessPred(BasicBlock *BB,<br>
ReturnInst *Ret, BasicBlock *&OldEntry,<br>
bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
bool CannotTailCallElimCallsMarkedTail);<br>
bool ProcessReturningBlock(ReturnInst *RI, BasicBlock *&OldEntry,<br>
bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
bool CannotTailCallElimCallsMarkedTail);<br>
bool CanMoveAboveCall(Instruction *I, CallInst *CI);<br>
Value *CanTransformAccumulatorRecursion(Instruction *I, CallInst *CI);<br>
@@ -445,7 +445,7 @@ TailCallElim::FindTRECandidate(Instructi<br>
bool TailCallElim::EliminateRecursiveTailCall(CallInst *CI, ReturnInst *Ret,<br>
BasicBlock *&OldEntry,<br>
bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
bool CannotTailCallElimCallsMarkedTail) {<br>
// If we are introducing accumulator recursion to eliminate operations after<br>
// the call instruction that are both associative and commutative, the initial<br>
@@ -621,7 +621,7 @@ bool TailCallElim::EliminateRecursiveTai<br>
bool TailCallElim::FoldReturnAndProcessPred(BasicBlock *BB,<br>
ReturnInst *Ret, BasicBlock *&OldEntry,<br>
bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
bool CannotTailCallElimCallsMarkedTail) {<br>
bool Change = false;<br>
<br>
@@ -655,10 +655,11 @@ bool TailCallElim::FoldReturnAndProcessP<br>
return Change;<br>
}<br>
<br>
-bool TailCallElim::ProcessReturningBlock(ReturnInst *Ret, BasicBlock *&OldEntry,<br>
- bool &TailCallsAreMarkedTail,<br>
- SmallVector<PHINode*, 8> &ArgumentPHIs,<br>
- bool CannotTailCallElimCallsMarkedTail) {<br>
+bool<br>
+TailCallElim::ProcessReturningBlock(ReturnInst *Ret, BasicBlock *&OldEntry,<br>
+ bool &TailCallsAreMarkedTail,<br>
+ SmallVectorImpl<PHINode *> &ArgumentPHIs,<br>
+ bool CannotTailCallElimCallsMarkedTail) {<br>
CallInst *CI = FindTRECandidate(Ret, CannotTailCallElimCallsMarkedTail);<br>
if (!CI)<br>
return false;<br>
<br>
Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Jul 13 23:42:23 2013<br>
@@ -3353,7 +3353,7 @@ static bool ForwardSwitchConditionToPHI(<br>
for (ForwardingNodesMap::iterator I = ForwardingNodes.begin(),<br>
E = ForwardingNodes.end(); I != E; ++I) {<br>
PHINode *Phi = I->first;<br>
- SmallVector<int,4> &Indexes = I->second;<br>
+ SmallVectorImpl<int> &Indexes = I->second;<br>
<br>
if (Indexes.size() < 2) continue;<br>
<br>
@@ -3438,11 +3438,12 @@ static Constant *ConstantFold(Instructio<br>
/// at the common destination basic block, *CommonDest, for one of the case<br>
/// destionations CaseDest corresponding to value CaseVal (0 for the default<br>
/// case), of a switch instruction SI.<br>
-static bool GetCaseResults(SwitchInst *SI,<br>
- ConstantInt *CaseVal,<br>
- BasicBlock *CaseDest,<br>
- BasicBlock **CommonDest,<br>
- SmallVector<std::pair<PHINode*,Constant*>, 4> &Res) {<br>
+static bool<br>
+GetCaseResults(SwitchInst *SI,<br>
+ ConstantInt *CaseVal,<br>
+ BasicBlock *CaseDest,<br>
+ BasicBlock **CommonDest,<br>
+ SmallVectorImpl<std::pair<PHINode*,Constant*> > &Res) {<br>
// The block from which we enter the common destination.<br>
BasicBlock *Pred = SI->getParent();<br>
<br>
@@ -3515,7 +3516,7 @@ namespace {<br>
SwitchLookupTable(Module &M,<br>
uint64_t TableSize,<br>
ConstantInt *Offset,<br>
- const SmallVector<std::pair<ConstantInt*, Constant*>, 4>& Values,<br>
+ const SmallVectorImpl<std::pair<ConstantInt*, Constant*> >& Values,<br>
Constant *DefaultValue,<br>
const DataLayout *TD);<br>
<br>
@@ -3562,7 +3563,7 @@ namespace {<br>
SwitchLookupTable::SwitchLookupTable(Module &M,<br>
uint64_t TableSize,<br>
ConstantInt *Offset,<br>
- const SmallVector<std::pair<ConstantInt*, Constant*>, 4>& Values,<br>
+ const SmallVectorImpl<std::pair<ConstantInt*, Constant*> >& Values,<br>
Constant *DefaultValue,<br>
const DataLayout *TD)<br>
: SingleValue(0), BitMap(0), BitMapElementTy(0), Array(0) {<br>
<br>
Modified: llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp Sat Jul 13 23:42:23 2013<br>
@@ -356,7 +356,7 @@ namespace {<br>
Instruction *J, unsigned o, bool IBeforeJ);<br>
<br>
void getReplacementInputsForPair(LLVMContext& Context, Instruction *I,<br>
- Instruction *J, SmallVector<Value *, 3> &ReplacedOperands,<br>
+ Instruction *J, SmallVectorImpl<Value *> &ReplacedOperands,<br>
bool IBeforeJ);<br>
<br>
void replaceOutputsOfPair(LLVMContext& Context, Instruction *I,<br>
@@ -2687,7 +2687,7 @@ namespace {<br>
// to the vector instruction that fuses I with J.<br>
void BBVectorize::getReplacementInputsForPair(LLVMContext& Context,<br>
Instruction *I, Instruction *J,<br>
- SmallVector<Value *, 3> &ReplacedOperands,<br>
+ SmallVectorImpl<Value *> &ReplacedOperands,<br>
bool IBeforeJ) {<br>
unsigned NumOperands = I->getNumOperands();<br>
<br>
<br>
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1088,7 +1088,7 @@ CodeGenRegBank::getCompositeSubRegIndex(<br>
}<br>
<br>
CodeGenSubRegIndex *CodeGenRegBank::<br>
-getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) {<br>
+getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {<br>
assert(Parts.size() > 1 && "Need two parts to concatenate");<br>
<br>
// Look for an existing entry.<br>
<br>
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)<br>
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Sat Jul 13 23:42:23 2013<br>
@@ -534,10 +534,10 @@ namespace llvm {<br>
// Find or create a sub-register index representing the concatenation of<br>
// non-overlapping sibling indices.<br>
CodeGenSubRegIndex *<br>
- getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&);<br>
+ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);<br>
<br>
void<br>
- addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts,<br>
+ addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,<br>
CodeGenSubRegIndex *Idx) {<br>
ConcatIdx.insert(std::make_pair(Parts, Idx));<br>
}<br>
<br>
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=186274&r1=186273&r2=186274&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=186274&r1=186273&r2=186274&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Sat Jul 13 23:42:23 2013<br>
@@ -1102,7 +1102,7 @@ void PredTransitions::getIntersectingVar<br>
TransVariant &Variant = Variants[VIdx];<br>
// Don't expand variants if the processor models don't intersect.<br>
// A zero processor index means any processor.<br>
- SmallVector<unsigned, 4> &ProcIndices = TransVec[TransIdx].ProcIndices;<br>
+ SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;<br>
if (ProcIndices[0] && Variants[VIdx].ProcIdx) {<br>
unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),<br>
Variant.ProcIdx);<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div>