<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div>The patch LGTM. I have a few comments:</div><div><br></div><div>This is a NOP:</div><div><br></div><div><div>+define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {</div><div>+entry:</div><div>+ %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0></div><div>+ ret <8 x i16> %shl</div><div>+}</div><div>+</div><div>+; CHECK: test_srlw_1:</div><div>+; CHECK: psrlw $0, %xmm0</div><div>+; CHECK-NEXT: ret</div><div>+</div></div><div><br></div><div>I think that this is also a missed optimization. 32 > 31. </div><div><br></div><div><div>+define <4 x i32> @test_srad_3(<4 x i32> %InVec) {</div><div>+entry:</div><div>+ %shl = ashr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32></div><div>+ ret <4 x i32> %shl</div><div>+}</div><div>+</div><div>+; CHECK: test_srad_3:</div><div>+; CHECK: psrad $32, %xmm0</div><div>+; CHECK-NEXT: ret</div></div><div><br></div><div><br></div><div>Nadav</div><div><br></div><div>On Jul 10, 2013, at 1:00 PM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:</div><div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Nadav might be someone good to review this.<br><br>-eric<br><br>On Wed, Jul 10, 2013 at 6:46 AM, <<a href="mailto:Andrea_DiBiagio@sn.scee.net">Andrea_DiBiagio@sn.scee.net</a>> wrote:<br><blockquote type="cite">Ping.<br><br>(See attached file: patch.diff)<br>Andrea DiBiagio/SN R&D/BS/UK/SCEE wrote on 01/07/2013 12:01:44:<br><br><blockquote type="cite">Friendly ping.<br><br><blockquote type="cite">From: Andrea DiBiagio/SN R&D/BS/UK/SCEE<br>Hi all,<br><br>I'd like to contribute a patch that teaches the x86 backend how to<br>combine SSE2/AVX2 packed logical shifts by immediate amount into<br>vectors of all 0s.<br><br>SSE2/AVX2 logical shift by immediate amount where the amount is<br>greater than or<br>equal to the vector element size always return a vector of all 0s.<br><br>Example:<br>pslld $35, %xmm0 # SSE2 packed doubleword logical shift left.<br> # %xmm0 is a vector of packed int (MVT::v4i32).<br><br>The shift from this example will return a vector of all zeros in %xmm0<br></blockquote></blockquote>and<br><blockquote type="cite"><blockquote type="cite">therefore it could be easily rewritten for example as:<br>xorps %xmm0, %xmm0<br><br>This patch adds a new target combine rule in X86ISelLowering.cpp to<br>make sure that we simplify when possible vector shifts into zero<br></blockquote></blockquote>vectors.<br><blockquote type="cite"><blockquote type="cite"><br>I added two new tests to verify that vector shifts are correctly folded<br></blockquote></blockquote>into<br><blockquote type="cite"><blockquote type="cite">vectors of all 0s when the immediate amount is equal or exceeds<br>the vector element size.<br><br>Thanks,<br>Andrea Di Biagio<br>SN Systems - Sony Computer Entertainment<br></blockquote></blockquote><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></blockquote></div></blockquote></div><br></body></html>