<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">It is not clear to me why this transformation is profitable for all platforms. You are adding an AND operation here. Should this optimization be target specific maybe ?<div><br><div><div>On Jun 21, 2013, at 11:45 AM, Michael Liao <<a href="mailto:michael.liao@intel.com">michael.liao@intel.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Author: hliao<br>Date: Fri Jun 21 13:45:27 2013<br>New Revision: 184575<br><br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=184575&view=rev">http://llvm.org/viewvc/llvm-project?rev=184575&view=rev</a><br>Log:<br>Fix PR16360<br><br>When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the<br>high bits are not cleared. Add 'and' to clear off them.<br><br><br>Added:<br> llvm/trunk/test/CodeGen/X86/pr16360.ll<br>Modified:<br> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br><br>Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=184575&r1=184574&r2=184575&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=184575&r1=184574&r2=184575&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 21 13:45:27 2013<br>@@ -3915,8 +3915,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N)<br> DAG.getConstant(~0ULL >> ShAmt, VT));<br> }<br><br>-<br>- // fold (srl (anyextend x), c) -> (anyextend (srl x, c))<br>+ // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)<br> if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {<br> // Shifting in all undef bits?<br> EVT SmallVT = N0.getOperand(0).getValueType();<br>@@ -3929,7 +3928,10 @@ SDValue DAGCombiner::visitSRL(SDNode *N)<br> N0.getOperand(0),<br> DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));<br> AddToWorkList(SmallShift.getNode());<br>- return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift);<br>+ APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()).lshr(ShiftAmt);<br>+ return DAG.getNode(ISD::AND, SDLoc(N), VT,<br>+ DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),<br>+ DAG.getConstant(Mask, VT));<br> }<br> }<br><br><br>Added: llvm/trunk/test/CodeGen/X86/pr16360.ll<br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr16360.ll?rev=184575&view=auto">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr16360.ll?rev=184575&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/pr16360.ll (added)<br>+++ llvm/trunk/test/CodeGen/X86/pr16360.ll Fri Jun 21 13:45:27 2013<br>@@ -0,0 +1,16 @@<br>+; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s<br>+<br>+define i64 @foo(i32 %sum) {<br>+entry:<br>+ %conv = sext i32 %sum to i64<br>+ %shr = lshr i64 %conv, 2<br>+ %or = or i64 4611686018360279040, %shr<br>+ ret i64 %or<br>+}<br>+<br>+; CHECK: foo<br>+; CHECK: shrl $2<br>+; CHECK: orl $-67108864<br>+; CHECK-NOT: movl $-1<br>+; CHECK: movl $1073741823<br>+; CHECK: ret<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></div></body></html>