<div dir="ltr">Hi Justin,<div><br></div><div>This commit is braking on ARM bots:</div><div><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/8969/steps/check-all/logs/Clang%3A%3Anvptx-inlineasm-ptx.c">http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/8969/steps/check-all/logs/Clang%3A%3Anvptx-inlineasm-ptx.c</a><br>
</div><div><br></div><div>cheers,</div><div>--renato</div><div><br></div><div><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On 21 June 2013 19:51, Justin Holewinski <span dir="ltr"><<a href="mailto:jholewinski@nvidia.com" target="_blank">jholewinski@nvidia.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jholewinski<br>
Date: Fri Jun 21 13:51:49 2013<br>
New Revision: 184579<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=184579&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=184579&view=rev</a><br>
Log:<br>
[NVPTX] Add support for selecting CUDA vs OCL mode based on triple<br>
<br>
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/ADT/Triple.h<br>
llvm/trunk/lib/Support/Triple.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTX.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll<br>
llvm/trunk/test/CodeGen/NVPTX/i1-global.ll<br>
llvm/trunk/test/CodeGen/NVPTX/i1-param.ll<br>
llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll<br>
llvm/trunk/test/CodeGen/NVPTX/refl1.ll<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/Triple.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/Triple.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/Triple.h Fri Jun 21 13:51:49 2013<br>
@@ -81,7 +81,8 @@ public:<br>
BGP,<br>
BGQ,<br>
Freescale,<br>
- IBM<br>
+ IBM,<br>
+ NVIDIA<br>
};<br>
enum OSType {<br>
UnknownOS,<br>
@@ -107,7 +108,9 @@ public:<br>
NaCl, // Native Client<br>
CNK, // BG/P Compute-Node Kernel<br>
Bitrig,<br>
- AIX<br>
+ AIX,<br>
+ CUDA, // NVIDIA CUDA<br>
+ NVCL // NVIDIA OpenCL<br>
};<br>
enum EnvironmentType {<br>
UnknownEnvironment,<br>
<br>
Modified: llvm/trunk/lib/Support/Triple.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/Triple.cpp (original)<br>
+++ llvm/trunk/lib/Support/Triple.cpp Fri Jun 21 13:51:49 2013<br>
@@ -104,6 +104,7 @@ const char *Triple::getVendorTypeName(Ve<br>
case BGQ: return "bgq";<br>
case Freescale: return "fsl";<br>
case IBM: return "ibm";<br>
+ case NVIDIA: return "nvidia";<br>
}<br>
<br>
llvm_unreachable("Invalid VendorType!");<br>
@@ -135,6 +136,8 @@ const char *Triple::getOSTypeName(OSType<br>
case CNK: return "cnk";<br>
case Bitrig: return "bitrig";<br>
case AIX: return "aix";<br>
+ case CUDA: return "cuda";<br>
+ case NVCL: return "nvcl";<br>
}<br>
<br>
llvm_unreachable("Invalid OSType");<br>
@@ -260,6 +263,7 @@ static Triple::VendorType parseVendor(St<br>
.Case("bgq", Triple::BGQ)<br>
.Case("fsl", Triple::Freescale)<br>
.Case("ibm", Triple::IBM)<br>
+ .Case("nvidia", Triple::NVIDIA)<br>
.Default(Triple::UnknownVendor);<br>
}<br>
<br>
@@ -287,6 +291,8 @@ static Triple::OSType parseOS(StringRef<br>
.StartsWith("cnk", Triple::CNK)<br>
.StartsWith("bitrig", Triple::Bitrig)<br>
.StartsWith("aix", Triple::AIX)<br>
+ .StartsWith("cuda", Triple::CUDA)<br>
+ .StartsWith("nvcl", Triple::NVCL)<br>
.Default(Triple::UnknownOS);<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTX.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.h?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.h?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTX.h (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTX.h Fri Jun 21 13:51:49 2013<br>
@@ -77,8 +77,7 @@ extern Target TheNVPTXTarget64;<br>
namespace NVPTX {<br>
enum DrvInterface {<br>
NVCL,<br>
- CUDA,<br>
- TEST<br>
+ CUDA<br>
};<br>
<br>
// A field inside TSFlags needs a shift and a mask. The usage is<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp Fri Jun 21 13:51:49 2013<br>
@@ -19,23 +19,18 @@<br>
<br>
using namespace llvm;<br>
<br>
-// Select Driver Interface<br>
-#include "llvm/Support/CommandLine.h"<br>
-namespace {<br>
-cl::opt<NVPTX::DrvInterface> DriverInterface(<br>
- cl::desc("Choose driver interface:"),<br>
- cl::values(clEnumValN(NVPTX::NVCL, "drvnvcl", "Nvidia OpenCL driver"),<br>
- clEnumValN(NVPTX::CUDA, "drvcuda", "Nvidia CUDA driver"),<br>
- clEnumValN(NVPTX::TEST, "drvtest", "Plain Test"), clEnumValEnd),<br>
- cl::init(NVPTX::NVCL));<br>
-}<br>
<br>
NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,<br>
const std::string &FS, bool is64Bit)<br>
: NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),<br>
SmVersion(20) {<br>
<br>
- drvInterface = DriverInterface;<br>
+ Triple T(TT);<br>
+<br>
+ if (T.getOS() == Triple::NVCL)<br>
+ drvInterface = NVPTX::NVCL;<br>
+ else<br>
+ drvInterface = NVPTX::CUDA;<br>
<br>
// Provide the default CPU if none<br>
std::string defCPU = "sm_20";<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/generic-to-nvvm.ll Fri Jun 21 13:51:49 2013<br>
@@ -1,6 +1,7 @@<br>
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
<br>
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"<br>
+target triple = "nvptx-nvidia-cuda"<br>
<br>
; Ensure global variables in address space 0 are promoted to address space 1<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/i1-global.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-global.ll?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-global.ll?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/i1-global.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/i1-global.ll Fri Jun 21 13:51:49 2013<br>
@@ -1,7 +1,7 @@<br>
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
<br>
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"<br>
-<br>
+target triple = "nvptx-nvidia-cuda"<br>
<br>
; CHECK: .visible .global .align 1 .u8 mypred<br>
@mypred = addrspace(1) global i1 true, align 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/i1-param.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-param.ll?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-param.ll?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/i1-param.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/i1-param.ll Fri Jun 21 13:51:49 2013<br>
@@ -1,6 +1,7 @@<br>
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
<br>
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"<br>
+target triple = "nvptx-nvidia-cuda"<br>
<br>
; Make sure predicate (i1) operands to kernels get expanded out to .u8<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/load-sext-i1.ll Fri Jun 21 13:51:49 2013<br>
@@ -1,7 +1,7 @@<br>
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
<br>
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"<br>
-<br>
+target triple = "nvptx-nvidia-cuda"<br>
<br>
define void @main(i1* %a1, i32 %a2, i32* %arg3) {<br>
; CHECK: ld.u8<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/refl1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/refl1.ll?rev=184579&r1=184578&r2=184579&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/refl1.ll?rev=184579&r1=184578&r2=184579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/refl1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/refl1.ll Fri Jun 21 13:51:49 2013<br>
@@ -1,4 +1,6 @@<br>
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
+<br>
+target triple = "nvptx-nvidia-cuda"<br>
<br>
; Function Attrs: nounwind<br>
; CHECK: .entry foo<br>
<br>
<br>
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</blockquote></div><br></div>