<p dir="ltr"><br>
On Jun 17, 2013 5:58 PM, "Evan Cheng" <<a href="mailto:evan.cheng@apple.com">evan.cheng@apple.com</a>> wrote:<br>
><br>
> Are you sure we don't use any debug info fidelity due to this change?</p>
<p dir="ltr">As sure as I can be with the testing I have available to me. Including the apple gdb 4.2 suite and Linux gdb 7.5 tests.</p>
<p dir="ltr">><br>
> Thanks,<br>
><br>
> Evan<br>
><br>
> On Jun 16, 2013, at 1:34 PM, David Blaikie <<a href="mailto:dblaikie@gmail.com">dblaikie@gmail.com</a>> wrote:<br>
><br>
> > Author: dblaikie<br>
> > Date: Sun Jun 16 15:34:15 2013<br>
> > New Revision: 184066<br>
> ><br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=184066&view=rev">http://llvm.org/viewvc/llvm-project?rev=184066&view=rev</a><br>
> > Log:<br>
> > Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions<br>
> ><br>
> > Rather than using the full power of target-specific addressing modes in<br>
> > DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This<br>
> > reduces the complexity of debug info handling down to two<br>
> > representations of values (reg+offset and frame index+offset) rather<br>
> > than three or four.<br>
> ><br>
> > Ideally we could ensure that frame indicies had been eliminated by the<br>
> > time we reached an assembly or dwarf generation, but I haven't spent the<br>
> > time to figure out where the FIs are leaking through into that & whether<br>
> > there's a good place to convert them. Some FI+offset=>reg+offset<br>
> > conversion is done (see PrologEpilogInserter, for example) which is<br>
> > necessary for some SelectionDAG assumptions about registers, I believe,<br>
> > but it might be possible to make this a more thorough conversion &<br>
> > ensure there are no remaining FIs no matter how instruction selection<br>
> > is performed.<br>
> ><br>
> > Modified:<br>
> > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp<br>
> > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp<br>
> > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
> > llvm/trunk/lib/CodeGen/InlineSpiller.cpp<br>
> > llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp<br>
> > llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp<br>
> > llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
> > llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
> > llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp<br>
> > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
> > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
> > llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll<br>
> > llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -42,6 +42,7 @@<br>
> > #include "llvm/Support/MathExtras.h"<br>
> > #include "llvm/Support/Timer.h"<br>
> > #include "llvm/Target/Mangler.h"<br>
> > +#include "llvm/Target/TargetFrameLowering.h"<br>
> > #include "llvm/Target/TargetInstrInfo.h"<br>
> > #include "llvm/Target/TargetLowering.h"<br>
> > #include "llvm/Target/TargetLoweringObjectFile.h"<br>
> > @@ -591,8 +592,17 @@ static bool emitDebugValueComment(const<br>
> > } else if (MI->getOperand(0).isCImm()) {<br>
> > MI->getOperand(0).getCImm()->getValue().print(OS, false /*isSigned*/);<br>
> > } else {<br>
> > - assert(MI->getOperand(0).isReg() && "Unknown operand type");<br>
> > - unsigned Reg = MI->getOperand(0).getReg();<br>
> > + unsigned Reg;<br>
> > + if (MI->getOperand(0).isReg()) {<br>
> > + Reg = MI->getOperand(0).getReg();<br>
> > + Deref = Offset != 0; // FIXME: use a better sentinel value so that deref<br>
> > + // of a reg with a zero offset is valid<br>
> > + } else {<br>
> > + assert(MI->getOperand(0).isFI() && "Unknown operand type");<br>
> > + const TargetFrameLowering *TFI = AP.TM.getFrameLowering();<br>
> > + Offset += TFI->getFrameIndexReference(*AP.MF, MI->getOperand(0).getIndex(), Reg);<br>
> > + Deref = true;<br>
> > + }<br>
> > if (Reg == 0) {<br>
> > // Suppress offset, it is not meaningful here.<br>
> > OS << "undef";<br>
> > @@ -600,8 +610,6 @@ static bool emitDebugValueComment(const<br>
> > AP.OutStreamer.EmitRawText(OS.str());<br>
> > return true;<br>
> > }<br>
> > - Deref = Offset != 0; // FIXME: use a better sentinel value so that deref of<br>
> > - // a reg with a zero offset is valid<br>
> > if (Deref)<br>
> > OS << '[';<br>
> > OS << AP.TM.getRegisterInfo()->getName(Reg);<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -1525,43 +1525,23 @@ DIE *CompileUnit::constructVariableDIE(D<br>
> > // Check if variable is described by a DBG_VALUE instruction.<br>
> > if (const MachineInstr *DVInsn = DV->getMInsn()) {<br>
> > bool updated = false;<br>
> > - if (DVInsn->getNumOperands() == 3) {<br>
> > - if (DVInsn->getOperand(0).isReg()) {<br>
> > - const MachineOperand RegOp = DVInsn->getOperand(0);<br>
> > - const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();<br>
> > - if (DVInsn->getOperand(1).isImm() &&<br>
> > - TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {<br>
> > - unsigned FrameReg = 0;<br>
> > - const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();<br>
> > - int Offset =<br>
> > - TFI->getFrameIndexReference(*Asm->MF,<br>
> > - DVInsn->getOperand(1).getImm(),<br>
> > - FrameReg);<br>
> > - MachineLocation Location(FrameReg, Offset);<br>
> > - addVariableAddress(DV, VariableDie, Location);<br>
> > -<br>
> > - } else if (RegOp.getReg())<br>
> > - addVariableAddress(DV, VariableDie,<br>
> > - MachineLocation(RegOp.getReg()));<br>
> > - updated = true;<br>
> > - }<br>
> > - else if (DVInsn->getOperand(0).isImm())<br>
> > - updated =<br>
> > - addConstantValue(VariableDie, DVInsn->getOperand(0),<br>
> > - DV->getType());<br>
> > - else if (DVInsn->getOperand(0).isFPImm())<br>
> > - updated =<br>
> > - addConstantFPValue(VariableDie, DVInsn->getOperand(0));<br>
> > - else if (DVInsn->getOperand(0).isCImm())<br>
> > - updated =<br>
> > - addConstantValue(VariableDie,<br>
> > - DVInsn->getOperand(0).getCImm(),<br>
> > - DV->getType().isUnsignedDIType());<br>
> > - } else {<br>
> > - addVariableAddress(DV, VariableDie,<br>
> > - Asm->getDebugValueLocation(DVInsn));<br>
> > + assert(DVInsn->getNumOperands() == 3);<br>
> > + if (DVInsn->getOperand(0).isReg()) {<br>
> > + const MachineOperand RegOp = DVInsn->getOperand(0);<br>
> > + if (int64_t Offset = DVInsn->getOperand(1).getImm()) {<br>
> > + MachineLocation Location(RegOp.getReg(), Offset);<br>
> > + addVariableAddress(DV, VariableDie, Location);<br>
> > + } else if (RegOp.getReg())<br>
> > + addVariableAddress(DV, VariableDie, MachineLocation(RegOp.getReg()));<br>
> > updated = true;<br>
> > - }<br>
> > + } else if (DVInsn->getOperand(0).isImm())<br>
> > + updated =<br>
> > + addConstantValue(VariableDie, DVInsn->getOperand(0), DV->getType());<br>
> > + else if (DVInsn->getOperand(0).isFPImm())<br>
> > + updated = addConstantFPValue(VariableDie, DVInsn->getOperand(0));<br>
> > + else if (DVInsn->getOperand(0).isCImm())<br>
> > + updated = addConstantValue(VariableDie, DVInsn->getOperand(0).getCImm(),<br>
> > + DV->getType().isUnsignedDIType());<br>
> > if (!updated) {<br>
> > // If variableDie is not updated then DBG_VALUE instruction does not<br>
> > // have valid variable info.<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -1170,10 +1170,7 @@ static DotDebugLocEntry getDebugLocEntry<br>
> > const MachineInstr *MI) {<br>
> > const MDNode *Var = MI->getOperand(MI->getNumOperands() - 1).getMetadata();<br>
> ><br>
> > - if (MI->getNumOperands() != 3) {<br>
> > - MachineLocation MLoc = Asm->getDebugValueLocation(MI);<br>
> > - return DotDebugLocEntry(FLabel, SLabel, MLoc, Var);<br>
> > - }<br>
> > + assert(MI->getNumOperands() == 3);<br>
> > if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {<br>
> > MachineLocation MLoc;<br>
> > // TODO: Currently an offset of 0 in a DBG_VALUE means<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -24,6 +24,7 @@<br>
> > #include "llvm/CodeGen/MachineDominators.h"<br>
> > #include "llvm/CodeGen/MachineFrameInfo.h"<br>
> > #include "llvm/CodeGen/MachineFunction.h"<br>
> > +#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
> > #include "llvm/CodeGen/MachineInstrBundle.h"<br>
> > #include "llvm/CodeGen/MachineLoopInfo.h"<br>
> > #include "llvm/CodeGen/MachineRegisterInfo.h"<br>
> > @@ -1123,15 +1124,10 @@ void InlineSpiller::spillAroundUses(unsi<br>
> > uint64_t Offset = MI->getOperand(1).getImm();<br>
> > const MDNode *MDPtr = MI->getOperand(2).getMetadata();<br>
> > DebugLoc DL = MI->getDebugLoc();<br>
> > - if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,<br>
> > - Offset, MDPtr, DL)) {<br>
> > - DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);<br>
> > - MachineBasicBlock *MBB = MI->getParent();<br>
> > - MBB->insert(MBB->erase(MI), NewDV);<br>
> > - } else {<br>
> > - DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);<br>
> > - MI->eraseFromParent();<br>
> > - }<br>
> > + DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);<br>
> > + MachineBasicBlock *MBB = MI->getParent();<br>
> > + BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE))<br>
> > + .addFrameIndex(StackSlot).addImm(Offset).addMetadata(MDPtr);<br>
> > continue;<br>
> > }<br>
> ><br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -921,17 +921,6 @@ void UserValue::insertDebugValue(Machine<br>
> > MachineOperand &Loc = locations[LocNo];<br>
> > ++NumInsertedDebugValues;<br>
> ><br>
> > - // Frame index locations may require a target callback.<br>
> > - if (Loc.isFI()) {<br>
> > - MachineInstr *MI = TII.emitFrameIndexDebugValue(*MBB->getParent(),<br>
> > - Loc.getIndex(), offset, variable,<br>
> > - findDebugLoc());<br>
> > - if (MI) {<br>
> > - MBB->insert(I, MI);<br>
> > - return;<br>
> > - }<br>
> > - }<br>
> > - // This is not a frame index, or the target is happy with a standard FI.<br>
> > BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))<br>
> > .addOperand(Loc).addImm(offset).addMetadata(variable);<br>
> > }<br>
> > @@ -992,4 +981,3 @@ void LiveDebugVariables::dump() {<br>
> > static_cast<LDVImpl*>(pImpl)->print(dbgs());<br>
> > }<br>
> > #endif<br>
> > -<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -777,7 +777,22 @@ void PEI::replaceFrameIndices(MachineFun<br>
> > bool DoIncr = true;<br>
> > for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br>
> > if (!MI->getOperand(i).isFI())<br>
> > - continue;<br>
> > + continue;<br>
> > +<br>
> > + // Frame indicies in debug values are encoded in a target independent<br>
> > + // way with simply the frame index and offset rather than any<br>
> > + // target-specific addressing mode.<br>
> > + if (MI->isDebugValue()) {<br>
> > + assert(i == 0 && "Frame indicies can only appear as the first "<br>
> > + "operand of a DBG_VALUE machine instruction");<br>
> > + unsigned Reg;<br>
> > + MachineOperand &Offset = MI->getOperand(1);<br>
> > + Offset.setImm(Offset.getImm() +<br>
> > + TFI->getFrameIndexReference(<br>
> > + Fn, MI->getOperand(0).getIndex(), Reg));<br>
> > + MI->getOperand(0).ChangeToRegister(Reg, false /*isDef*/);<br>
> > + continue;<br>
> > + }<br>
> ><br>
> > // Some instructions (e.g. inline asm instructions) can have<br>
> > // multiple frame indices and/or cause eliminateFrameIndex<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -297,25 +297,21 @@ void RAFast::spillVirtReg(MachineBasicBl<br>
> > LiveDbgValueMap[LRI->VirtReg];<br>
> > for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {<br>
> > MachineInstr *DBG = LRIDbgValues[li];<br>
> > - const MDNode *MDPtr =<br>
> > - DBG->getOperand(DBG->getNumOperands()-1).getMetadata();<br>
> > - int64_t Offset = 0;<br>
> > - if (DBG->getOperand(1).isImm())<br>
> > - Offset = DBG->getOperand(1).getImm();<br>
> > + const MDNode *MDPtr = DBG->getOperand(2).getMetadata();<br>
> > + int64_t Offset = DBG->getOperand(1).getImm();<br>
> > DebugLoc DL;<br>
> > if (MI == MBB->end()) {<br>
> > // If MI is at basic block end then use last instruction's location.<br>
> > MachineBasicBlock::iterator EI = MI;<br>
> > DL = (--EI)->getDebugLoc();<br>
> > - }<br>
> > - else<br>
> > + } else<br>
> > DL = MI->getDebugLoc();<br>
> > - if (MachineInstr *NewDV =<br>
> > - TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {<br>
> > - MachineBasicBlock *MBB = DBG->getParent();<br>
> > - MBB->insert(MI, NewDV);<br>
> > - DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);<br>
> > - }<br>
> > + MachineBasicBlock *MBB = DBG->getParent();<br>
> > + MachineInstr *NewDV =<br>
> > + BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))<br>
> > + .addFrameIndex(FI).addImm(Offset).addMetadata(MDPtr);<br>
> > + (void)NewDV;<br>
> > + DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);<br>
> > }<br>
> > // Now this register is spilled there is should not be any DBG_VALUE<br>
> > // pointing to this register because they are all pointing to spilled value<br>
> > @@ -863,21 +859,16 @@ void RAFast::AllocateBasicBlock() {<br>
> > const MDNode *MDPtr =<br>
> > MI->getOperand(MI->getNumOperands()-1).getMetadata();<br>
> > DebugLoc DL = MI->getDebugLoc();<br>
> > - if (MachineInstr *NewDV =<br>
> > - TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {<br>
> > - DEBUG(dbgs() << "Modifying debug info due to spill:" <<<br>
> > - "\t" << *MI);<br>
> > - MachineBasicBlock *MBB = MI->getParent();<br>
> > - MBB->insert(MBB->erase(MI), NewDV);<br>
> > - // Scan NewDV operands from the beginning.<br>
> > - MI = NewDV;<br>
> > - ScanDbgValue = true;<br>
> > - break;<br>
> > - } else {<br>
> > - // We can't allocate a physreg for a DebugValue; sorry!<br>
> > - DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");<br>
> > - MO.setReg(0);<br>
> > - }<br>
> > + MachineBasicBlock *MBB = MI->getParent();<br>
> > + MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL,<br>
> > + TII->get(TargetOpcode::DBG_VALUE))<br>
> > + .addFrameIndex(SS).addImm(Offset).addMetadata(MDPtr);<br>
> > + DEBUG(dbgs() << "Modifying debug info due to spill:"<br>
> > + << "\t" << *NewDV);<br>
> > + // Scan NewDV operands from the beginning.<br>
> > + MI = NewDV;<br>
> > + ScanDbgValue = true;<br>
> > + break;<br>
> > }<br>
> > }<br>
> > LiveDbgValueMap[Reg].push_back(MI);<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -41,6 +41,7 @@<br>
> ><br>
> > #define DEBUG_TYPE "isel"<br>
> > #include "llvm/CodeGen/FastISel.h"<br>
> > +#include "llvm/ADT/Optional.h"<br>
> > #include "llvm/ADT/Statistic.h"<br>
> > #include "llvm/Analysis/Loads.h"<br>
> > #include "llvm/CodeGen/Analysis.h"<br>
> > @@ -613,16 +614,14 @@ bool FastISel::SelectCall(const User *I)<br>
> > return true;<br>
> > }<br>
> ><br>
> > - unsigned Reg = 0;<br>
> > - unsigned Offset = 0;<br>
> > - if (const Argument *Arg = dyn_cast<Argument>(Address)) {<br>
> > + Optional<MachineOperand> Op;<br>
> > + if (const Argument *Arg = dyn_cast<Argument>(Address))<br>
> > // Some arguments' frame index is recorded during argument lowering.<br>
> > - Offset = FuncInfo.getArgumentFrameIndex(Arg);<br>
> > - if (Offset)<br>
> > - Reg = TRI.getFrameRegister(*FuncInfo.MF);<br>
> > - }<br>
> > - if (!Reg)<br>
> > - Reg = lookUpRegForValue(Address);<br>
> > + if (int FI = FuncInfo.getArgumentFrameIndex(Arg))<br>
> > + Op = MachineOperand::CreateFI(FI);<br>
> > + if (!Op)<br>
> > + if (unsigned Reg = lookUpRegForValue(Address))<br>
> > + Op = MachineOperand::CreateReg(Reg, false);<br>
> ><br>
> > // If we have a VLA that has a "use" in a metadata node that's then used<br>
> > // here but it has no other uses, then we have a problem. E.g.,<br>
> > @@ -635,16 +634,19 @@ bool FastISel::SelectCall(const User *I)<br>
> > // If we assign 'a' a vreg and fast isel later on has to use the selection<br>
> > // DAG isel, it will want to copy the value to the vreg. However, there are<br>
> > // no uses, which goes counter to what selection DAG isel expects.<br>
> > - if (!Reg && !Address->use_empty() && isa<Instruction>(Address) &&<br>
> > + if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&<br>
> > (!isa<AllocaInst>(Address) ||<br>
> > !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))<br>
> > - Reg = FuncInfo.InitializeRegForValue(Address);<br>
> > + Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),<br>
> > + false);<br>
> > +<br>
> > + if (Op && Op->isReg())<br>
> > + Op->setIsDebug(true);<br>
> ><br>
> > - if (Reg)<br>
> > + if (Op)<br>
> > BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,<br>
> > - TII.get(TargetOpcode::DBG_VALUE))<br>
> > - .addReg(Reg, RegState::Debug).addImm(Offset)<br>
> > - .addMetadata(DI->getVariable());<br>
> > + TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)<br>
> > + .addMetadata(DI->getVariable());<br>
> > else<br>
> > // We can't yet handle anything else here because it would require<br>
> > // generating code, thus altering codegen because of debug info.<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -639,8 +639,8 @@ InstrEmitter::EmitDbgValue(SDDbgValue *S<br>
> > if (SD->getKind() == SDDbgValue::FRAMEIX) {<br>
> > // Stack address; this needs to be lowered in target-dependent fashion.<br>
> > // EmitTargetCodeForFrameDebugValue is responsible for allocation.<br>
> > - unsigned FrameIx = SD->getFrameIx();<br>
> > - return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);<br>
> > + return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))<br>
> > + .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);<br>
> > }<br>
> > // Otherwise, we're going to create an instruction here.<br>
> > const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);<br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -15,6 +15,7 @@<br>
> > #include "SelectionDAGBuilder.h"<br>
> > #include "SDNodeDbgValue.h"<br>
> > #include "llvm/ADT/BitVector.h"<br>
> > +#include "llvm/ADT/Optional.h"<br>
> > #include "llvm/ADT/SmallSet.h"<br>
> > #include "llvm/Analysis/AliasAnalysis.h"<br>
> > #include "llvm/Analysis/BranchProbabilityInfo.h"<br>
> > @@ -4349,20 +4350,19 @@ SelectionDAGBuilder::EmitFuncArgumentDbg<br>
> ><br>
> > MachineFunction &MF = DAG.getMachineFunction();<br>
> > const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();<br>
> > - const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();<br>
> ><br>
> > // Ignore inlined function arguments here.<br>
> > DIVariable DV(Variable);<br>
> > if (DV.isInlinedFnArgument(MF.getFunction()))<br>
> > return false;<br>
> ><br>
> > - unsigned Reg = 0;<br>
> > + Optional<MachineOperand> Op;<br>
> > // Some arguments' frame index is recorded during argument lowering.<br>
> > - Offset = FuncInfo.getArgumentFrameIndex(Arg);<br>
> > - if (Offset)<br>
> > - Reg = TRI->getFrameRegister(MF);<br>
> > + if (int FI = FuncInfo.getArgumentFrameIndex(Arg))<br>
> > + Op = MachineOperand::CreateFI(FI);<br>
> ><br>
> > - if (!Reg && N.getNode()) {<br>
> > + if (!Op && N.getNode()) {<br>
> > + unsigned Reg;<br>
> > if (N.getOpcode() == ISD::CopyFromReg)<br>
> > Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();<br>
> > else<br>
> > @@ -4373,32 +4373,33 @@ SelectionDAGBuilder::EmitFuncArgumentDbg<br>
> > if (PR)<br>
> > Reg = PR;<br>
> > }<br>
> > + if (Reg)<br>
> > + Op = MachineOperand::CreateReg(Reg, false);<br>
> > }<br>
> ><br>
> > - if (!Reg) {<br>
> > + if (!Op) {<br>
> > // Check if ValueMap has reg number.<br>
> > DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);<br>
> > if (VMI != FuncInfo.ValueMap.end())<br>
> > - Reg = VMI->second;<br>
> > + Op = MachineOperand::CreateReg(VMI->second, false);<br>
> > }<br>
> ><br>
> > - if (!Reg && N.getNode()) {<br>
> > + if (!Op && N.getNode())<br>
> > // Check if frame index is available.<br>
> > if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))<br>
> > if (FrameIndexSDNode *FINode =<br>
> > - dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {<br>
> > - Reg = TRI->getFrameRegister(MF);<br>
> > - Offset = FINode->getIndex();<br>
> > - }<br>
> > - }<br>
> > + dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))<br>
> > + Op = MachineOperand::CreateFI(FINode->getIndex());<br>
> ><br>
> > - if (!Reg)<br>
> > + if (!Op)<br>
> > return false;<br>
> ><br>
> > - MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),<br>
> > - TII->get(TargetOpcode::DBG_VALUE))<br>
> > - .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);<br>
> > - FuncInfo.ArgDbgValues.push_back(&*MIB);<br>
> > + if (Op->isReg())<br>
> > + Op->setIsDebug();<br>
> > +<br>
> > + FuncInfo.ArgDbgValues.push_back(<br>
> > + BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))<br>
> > + .addOperand(*Op).addImm(Offset).addMetadata(Variable));<br>
> > return true;<br>
> > }<br>
> ><br>
> ><br>
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)<br>
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -401,7 +401,8 @@ bool SelectionDAGISel::runOnMachineFunct<br>
> > // Insert DBG_VALUE instructions for function arguments to the entry block.<br>
> > for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {<br>
> > MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];<br>
> > - unsigned Reg = MI->getOperand(0).getReg();<br>
> > + bool hasFI = MI->getOperand(0).isFI();<br>
> > + unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();<br>
> > if (TargetRegisterInfo::isPhysicalRegister(Reg))<br>
> > EntryMBB->insert(EntryMBB->begin(), MI);<br>
> > else {<br>
> > @@ -414,6 +415,8 @@ bool SelectionDAGISel::runOnMachineFunct<br>
> > // If Reg is live-in then update debug info to track its copy in a vreg.<br>
> > DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);<br>
> > if (LDI != LiveInMap.end()) {<br>
> > + assert(!hasFI && "There's no handling of frame pointer updating here yet "<br>
> > + "- add if needed");<br>
> > MachineInstr *Def = RegInfo->getVRegDef(LDI->second);<br>
> > MachineBasicBlock::iterator InsertPos = Def;<br>
> > const MDNode *Variable =<br>
> ><br>
> > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)<br>
> > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sun Jun 16 15:34:15 2013<br>
> > @@ -702,12 +702,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex<br>
> > }<br>
> > #endif // NDEBUG<br>
> ><br>
> > - // Special handling of dbg_value instructions.<br>
> > - if (MI.isDebugValue()) {<br>
> > - MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);<br>
> > - MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);<br>
> > - return;<br>
> > - }<br>
> > + assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");<br>
> ><br>
> > // Modify MI as necessary to handle as much of 'Offset' as possible<br>
> > bool Done = false;<br>
> ><br>
> > Modified: llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll (original)<br>
> > +++ llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll Sun Jun 16 15:34:15 2013<br>
> > @@ -11,7 +11,7 @@ define void @foo(%struct.tag_s* nocaptur<br>
> > tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !13), !dbg !21<br>
> > tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !14), !dbg !22<br>
> > tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !17), !dbg !23<br>
> > -;CHECK: @DEBUG_VALUE: foo:y <- [R7+4294967295]<br>
> > +;CHECK: @DEBUG_VALUE: foo:y <- [R7+8]<br>
> > tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !18), !dbg !24<br>
> > tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !19), !dbg !25<br>
> > %1 = icmp eq %struct.tag_s* %c, null, !dbg !26<br>
> ><br>
> > Modified: llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll<br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=184066&r1=184065&r2=184066&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=184066&r1=184065&r2=184066&view=diff</a><br>
> > ==============================================================================<br>
> > --- llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll (original)<br>
> > +++ llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll Sun Jun 16 15:34:15 2013<br>
> > @@ -1,5 +1,5 @@<br>
> > ; RUN: llc -O0 < %s | FileCheck %s<br>
> > -; CHECK: @DEBUG_VALUE: mydata <- [sp+#{{[0-9]+}}]+#0<br>
> > +; CHECK: @DEBUG_VALUE: mydata <- [SP+{{[0-9]+}}]<br>
> > ; Radar 9331779<br>
> > target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"<br>
> > target triple = "thumbv7-apple-ios"<br>
> ><br>
> ><br>
> > _______________________________________________<br>
> > llvm-commits mailing list<br>
> > <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
><br>
</p>