<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Matt, <div><br></div><div>Can you attach the test cases to this patch and add the description ? It will make it easier for me to review it. </div><div><br></div><div>Thanks,</div><div>Nadav</div><div><div><div>On Jun 3, 2013, at 1:43 PM, Matt Arsenault <<a href="mailto:Matthew.Arsenault@amd.com">Matthew.Arsenault@amd.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"> Remove PromoteVectorOp part<br><br>Hi nadav,<br><br><a href="http://llvm-reviews.chandlerc.com/D903">http://llvm-reviews.chandlerc.com/D903</a><br><br>CHANGE SINCE LAST DIFF<br> <a href="http://llvm-reviews.chandlerc.com/D903?vs=2217&id=2253#toc">http://llvm-reviews.chandlerc.com/D903?vs=2217&id=2253#toc</a><br><br>Files:<br> lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br> lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp<br> lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br> lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br><br>Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>===================================================================<br>--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>@@ -3659,16 +3659,28 @@<br> Tmp3 = Node->getOperand(2); // True<br> Tmp4 = Node->getOperand(3); // False<br> SDValue CC = Node->getOperand(4);<br>+ ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();<br>+ EVT LHSVT = Tmp1.getValueType();<br>+ EVT LSetCCType = getSetCCResultType(LHSVT);<br>+<br>+ if (TLI.getCondCodeAction(CCCode, LSetCCType.getSimpleVT())<br>+ == TargetLowering::Legal) {<br>+ // The condition is legal, lets expand into setcc + [v]select.<br>+ Tmp1 = DAG.getSetCC(dl, LSetCCType, Tmp1, Tmp2, CCCode);<br>+ Tmp1 = DAG.getSelect(dl, Node->getValueType(0), Tmp1, Tmp3, Tmp4);<br>+ } else {<br>+ LegalizeSetCCCondCode(LSetCCType.getSimpleVT(),<br>+ Tmp1, Tmp2, CC, dl);<br>+ // The condition is illegal, but we have a valid convesions.<br>+ // Lets convert to SELECT_CC with a legal CC.<br>+ assert(!Tmp2.getNode() &&<br>+ "Can't legalize SELECT_CC with legal condition!");<br><br>- LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),<br>- Tmp1, Tmp2, CC, dl);<br>+ Tmp2 = DAG.getConstant(0, LHSVT);<br>+ Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2,<br>+ Tmp3, Tmp4, ISD::SETNE);<br>+ }<br><br>- assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");<br>- Tmp2 = DAG.getConstant(0, Tmp1.getValueType());<br>- CC = DAG.getCondCode(ISD::SETNE);<br>- Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,<br>- Tmp3, Tmp4, CC);<br>- Results.push_back(Tmp1);<br> break;<br> }<br> case ISD::BR_CC: {<br>@@ -3826,8 +3838,15 @@<br> case ISD::XOR: {<br> unsigned ExtOp, TruncOp;<br> if (OVT.isVector()) {<br>- ExtOp = ISD::BITCAST;<br>- TruncOp = ISD::BITCAST;<br>+ if (OVT.getSizeInBits() == NVT.getSizeInBits()) {<br>+ ExtOp = ISD::BITCAST;<br>+ TruncOp = ISD::BITCAST;<br>+ } else if (OVT.getVectorNumElements() == NVT.getVectorNumElements()) {<br>+ ExtOp = ISD::SIGN_EXTEND;<br>+ TruncOp = ISD::TRUNCATE;<br>+ } else {<br>+ llvm_unreachable("Cannot determine what operations to execute!");<br>+ }<br> } else {<br> assert(OVT.isInteger() && "Cannot promote logic operation");<br> ExtOp = ISD::ANY_EXTEND;<br>Index: lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp<br>===================================================================<br>--- lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp<br>+++ lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp<br>@@ -490,10 +490,10 @@<br> SDValue Cond = N->getOperand(0);<br> CL = CH = Cond;<br> if (Cond.getValueType().isVector()) {<br>- assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&<br>- "Condition legalized before result?");<br>- unsigned NumElements = Cond.getValueType().getVectorNumElements();<br>- EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);<br>+ EVT CondVT = Cond.getValueType();<br>+ unsigned NumElements = CondVT.getVectorNumElements();<br>+ EVT VCondTy = EVT::getVectorVT(*DAG.getContext(),<br>+ CondVT.getVectorElementType(), NumElements / 2);<br> CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,<br> DAG.getIntPtrConstant(0));<br> CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,<br>Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>===================================================================<br>--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>@@ -268,9 +268,13 @@<br> case TargetLowering::ZeroOrNegativeOneBooleanContent:<br> assert(VecBool == TargetLowering::UndefinedBooleanContent ||<br> VecBool == TargetLowering::ZeroOrOneBooleanContent);<br>- // Vector reads from a one, scalar from all ones so sign extend.<br>- Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,<br>- Cond, DAG.getValueType(MVT::i1));<br>+<br>+ if (CondVT.getScalarType() == MVT::i1) {<br>+ // Vector reads from a one, scalar from all ones so sign extend.<br>+ Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,<br>+ Cond, DAG.getValueType(MVT::i1));<br>+ }<br>+<br> break;<br> }<br> }<br>@@ -307,7 +311,8 @@<br> SDLoc DL(N);<br><br> // Turn it into a scalar SETCC.<br>- return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));<br>+ return DAG.getNode(ISD::SETCC, DL, N->getValueType(0),<br>+ LHS, RHS, N->getOperand(2));<br>}<br><br>SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {<br>@@ -334,7 +339,7 @@<br> SDLoc DL(N);<br><br> // Turn it into a scalar SETCC.<br>- SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,<br>+ SDValue Res = DAG.getNode(ISD::SETCC, DL, NVT, LHS, RHS,<br> N->getOperand(2));<br> // Vectors may have a different boolean contents to scalars. Promote the<br> // value appropriately.<br>Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>===================================================================<br>--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>@@ -1766,6 +1766,8 @@<br> return;<br> }<br> case ISD::SELECT:<br>+ assert(!Op.getOperand(0).getValueType().isVector() &&<br>+ "Should use ISD::VSELECT for vector select!");<br> ComputeMaskedBits(Op.getOperand(2), KnownZero, KnownOne, Depth+1);<br> ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);<br> assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");<br>@@ -3290,6 +3292,8 @@<br> break;<br> }<br> case ISD::SELECT:<br>+ assert(!N1.getValueType().isVector() &&<br>+ "Should use ISD::VSELECT for vector select!");<br> if (N1C) {<br> if (N1C->getZExtValue())<br> return N2; // select true, X, Y -> X<br><span><D903.2.patch></span></div></blockquote></div><br></div></body></html>