<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On May 13, 2013, at 10:42 AM, Krzysztof Parzyszek <<a href="mailto:kparzysz@codeaurora.org">kparzysz@codeaurora.org</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">On 5/13/2013 12:18 PM, Tom Stellard wrote:<br><blockquote type="cite"><br>We have the exact same problem for the VLIW4/5 subtargets in R600.<br>Instructions that write to different sub registers of the same super<br>register cannot be scheduled together in the same packet. Vincent has<br>written a patch to fix this in LLVM core. The latest version that was sent<br>to the list is here:<br><a href="http://permalink.gmane.org/gmane.comp.compilers.llvm.cvs/141708">http://permalink.gmane.org/gmane.comp.compilers.llvm.cvs/141708</a><br><br>But Vincent may be able to point you to a more up to date version.<br></blockquote><br>The original intent of this patch was that it will eventually be eliminated when the liveness analysis tracks register lanes. I haven't looked at the patch, but is that what it tries to do?<br><br>We've had this one running for over 6 months and we would need to make sure that we still get the performance with any potential replacement.<br><br>-Krzysztof<br><br></div></blockquote><br></div><div><div>The only good machine independent fix for this is to eliminate the</div><div>imp-use/imp-def operands. But that has to be done carefully to avoid</div><div>breaking existing postRA passes.</div><div><br></div><div>A good target-specific workaround for this is to follow Vincent's</div><div>approach of modifying the scheduling DAG after it is built.</div><div><br></div><div>Vincent's approach worked for vregs and is needed until we track</div><div>subreg liveness on vregs. You could implement a similar workaround for</div><div>physregs until the imp-def/use operands can be properly removed.</div><div><br></div><div>An even quicker hack is for a Hexagon-specific postRA pass to remove</div><div>the imp-def/use operands in certain cases. Mostly what will break is</div><div>verification, which you could disable. There may be some danger if</div><div>you're using the RegScavenger code. I would consult with Jakob before</div><div>actually relying on that.</div><div><br></div><div>Your current approach misinterprets the meaning of "undef", which is</div><div>unsafe to expose to other targets. Undefs can't generally be ignored,</div><div>it just conveniently disables verification.</div><div><br></div><div>-Andy</div></div></body></html>