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<div class="moz-cite-prefix"><tt>LGTM. Please go ahead and commit.</tt><tt><br>
</tt><tt><br>
</tt><tt>-Anshu</tt><tt><br>
</tt><tt><br>
</tt><tt>---
</tt><tt><br>
</tt><tt>Qualcomm Innovation Center, Inc. is a member of Code
Aurora Forum, hosted by The Linux Foundation<br>
<br>
</tt><tt></tt>
<tt><br>
</tt><tt>On 5/2/2013 2:24 PM, Pranav Bhandarkar wrote:</tt><tt><br>
</tt></div>
<blockquote cite="mid:5182BD85.5010106@codeaurora.org" type="cite"><tt>Hi,
</tt><tt><br>
</tt>
<tt><br>
</tt><tt>This patch adds a peephole optimizations for zero_extends
(i32->i64).
</tt><tt><br>
</tt>
<tt><br>
</tt><tt>It does two types of optimizations.
</tt><tt><br>
</tt><tt>1) Converts
</tt><tt><br>
</tt><tt> "
</tt><tt><br>
</tt><tt> vreg_i64 = combine (#0, vreg_i32)
</tt><tt><br>
</tt><tt> ..... = vreg_i64:subreg_loreg
</tt><tt><br>
</tt><tt> "
</tt><tt><br>
</tt><tt> into
</tt><tt><br>
</tt><tt> "
</tt><tt><br>
</tt><tt> vreg_i64 = combine (#0, vreg_i32)
</tt><tt><br>
</tt><tt> ..... = vreg_i32.
</tt><tt><br>
</tt><tt> "
</tt><tt><br>
</tt>
<tt><br>
</tt><tt>2) Adds patterns in the td file to convert
</tt><tt><br>
</tt><tt> " (i64 (zero_extend i32 vreg_i32)) | (shl
vreg_i64, 32) "
</tt><tt><br>
</tt><tt> into a Hexgaon MI
</tt><tt><br>
</tt><tt> " combine_rr (vreg_i64:subreg_loreg, vreg_i32) "
</tt><tt><br>
</tt>
<tt><br>
</tt><tt>Jyotsna, Anshu: Ok to commit ?
</tt><tt><br>
</tt>
<tt><br>
</tt><tt>Thanks,
</tt><tt><br>
</tt><tt>Pranav
</tt><tt><br>
</tt>
<tt><br>
</tt><tt><br>
</tt>
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<tt><br>
</tt>
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</blockquote>
<tt><br>
</tt>
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