<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">LGTM. There’s already a similar hack in there for the _PRE_REG version.<div><br></div><div>-j</div><div><br><div><div>On Apr 29, 2013, at 5:42 AM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">*pokes Jim*<br><br>Jim?<br><br>-eric<br><br>On Mon, Apr 29, 2013 at 11:39 AM, Mihail Popa <<a href="mailto:mihail.popa@gmail.com">mihail.popa@gmail.com</a>> wrote:<br><blockquote type="cite">Guys, may I commit this?<br><br>The absence of this additional constraint triggers an unfortunate behaviour<br>in the disassembler. For example:<br><br>echo "0xb0 0x00 0x10 0xe6" | llvm-mc -disassemble -show-inst -triple=armv7<br>-show-encoding<br><br>ldr r0, [r0], -r0, lsr #1 @ encoding: [0xa0,0x00,0x10,0xe6]<br> @ <MCInst #205 LDR_POST_REG<br> @ <MCOperand Reg:60><br> @ <MCOperand Reg:60><br> @ <MCOperand Reg:60><br> @ <MCOperand Reg:60><br> @ <MCOperand Imm:159745><br> @ <MCOperand Imm:14><br> @ <MCOperand Reg:0>><br><br>Note the input and output encodings differ! This is because the input<br>encoding is actually undefined but accepted as a LDR.<br>We don't want that in a disassembler. I can also produce about 15 million<br>additional similar failures due to this oversight alone!<br><br>Thanks,<br>Mihai<br><br><br><br>On Fri, Apr 26, 2013 at 5:59 PM, Owen Anderson <<a href="mailto:resistor@mac.com">resistor@mac.com</a>> wrote:<br><blockquote type="cite"><br>It looks OK to me offhand, but I have no memory of why the test was<br>XFAIL'd initially.<br><br>--Owen<br><br>On Apr 26, 2013, at 8:54 AM, Rafael Espíndola <<a href="mailto:rafael.espindola@gmail.com">rafael.espindola@gmail.com</a>><br>wrote:<br><br><blockquote type="cite">Owen, this patch looks good to me, but it has been disabled since the<br>switch to the new arm disassembler. Would you mind double checking<br>that it is the correct fix?<br><br>On 26 April 2013 11:46, Mihail Popa <<a href="mailto:mihail.popa@arm.com">mihail.popa@arm.com</a>> wrote:<br><blockquote type="cite">Hello.<br><br>This tightens up the encoding description for ARM post-indexed ldr<br>instructions. All instructions in this class have bit 4 cleared. It<br>turns<br>out that there is a test case for this, but it was marked XFAIL.<br><br>Regards,<br>Mihai<br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br><br></blockquote></blockquote><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote><br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</blockquote></div></blockquote></div><br></div></body></html>