<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Apr 16, 2013, at 6:34 PM, Michael Liao <<a href="mailto:michael.liao@intel.com">michael.liao@intel.com</a>> wrote:</div><br><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">an alternative approach is proposed to refactor atomic<br>instruction code generation, enable HLE hint to be passed into backend<br>and hence enable HLE code generation.<br></div></blockquote><div><br></div><div>Hi Michael, </div><div><br></div><div>Thanks for working on this, but I really prefer that you discuss your proposal with the mailing list before you send patches. You are putting the reviewers in a position where its difficult to make suggestions or propose alternatives. This is especially important for such intrusive patches. </div><div><br></div><div>Last time you sent the HLE patches I suggested that you implement HLE as intrinsics. I don't understand why HLE needs to be more than a group of intrinsics, from start-to-finish. Why do you need code other than intrinsics ? </div><div><br></div><div>Target specific intrinsics will allow HLE-aware synchronization library writers and researchers who implement alternative programming models to use HLE. </div><div><br></div><div>Thanks,</div><div>Nadav</div><div><br></div><br><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">To add minimal dependence on SelectionDAG (as we have no way to bypass<br>it completely), this proposal adds series intrinsics mapping to native<br>atomic intrinsics, e.g. llvm.x86.cas.* to x86's CMPXCHG and adds a pass<br>just before instruction selection to transform all atomic instructions<br>into target-specific native intrinsics. For atomic instructions not<br>supported directly by hardware, that pass will transform it into CAS<br>(compare-and-swap) loop or LLSC (load-link & store conditional) loop<br>after enquiring target. E.g. atomicrmw max %Ptr, %Val is not directly<br>supported, it will be translated into CAS loop or LLSC loop as follows:<br><br>---- CAS loop ----<br>Orig := load(Ptr);<br>do {<br> Old := PHI(Orig, Curr);<br> New := max(Old, New);<br> {Curr, Flag} = CAS(Ptr, Old, New);<br>} while (!Flag);<br>v := Curr;<br><br>where {Curr, Flag} is the return value of CAS, Curr is the current value<br>in that memory and Flag indicates whether the New value is stored in<br>that location.<br><br>---- LLSC loop ----<br>do {<br> Curr := LL(Ptr);<br> New := max(Old, New);<br> Flag := SC(Ptr, New);<br>} while (!Flag);<br>v := Curr;<br><br>where Flag indicates whether the SC succeeds.<br><br>(LLSC is available for most RISC targets. x86 has CAS only.)<br><br>With this atomic IR lower pass, all atomic instructions are translated<br>into target native intrinsic or code sequence based them. To get HLE<br>supported, target native intrinsics will be extended with one extra<br>parameter, HLE hint. Targets supporting HLE will lower them<br>correspondingly following target ISA spec.<br><br>Before completing the full patch, I attached the early patchs for review<br>and demonstration purpose.<br><br>- 0001-Add-CAS-intrinsic-to-help-refactoring-Atomic-support.patch<br> This patch adds llvm.x86.cas.* and llvm.x86.dcas.*, which will be<br>mapped to CMPXCHG, CMPXCHG8B, CMPXCHG16B separately.<br><br>- 0002-Add-X86-atomic-IR-lower-pass.patch<br> This patch adds a pre-isel pass to lower all atomic instructions into<br>target native intrinsics or CAS/LLSC loops.<br><br>- 0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch<br> This patch adds X86 HLE instruction encoding and assembler support.<br><br>- 0004-Add-HLE-code-generation.patch<br> This patch extends X86 native intrinsics to propagate HLE hint and<br>enable HLE code generation.<br><br>A early test case (hle-atomic-max.ll) is also added for your reference.<br><br>Thanks for review<br>- Michael<br><br><br><br><span><0001-Add-CAS-intrinsic-to-help-refactoring-Atomic-support.patch></span><span><0002-Add-X86-atomic-IR-lower-pass.patch></span><span><0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch></span><span><0004-Add-HLE-code-generation.patch></span><span><hle-atomic-max.ll></span>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></body></html>