<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Oh yes, I see. I read the code and it LGTM. Thanks Michael.<div><br><div><div>On Apr 10, 2013, at 9:17 PM, Michael Liao <<a href="mailto:michael.liao@intel.com">michael.liao@intel.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Hi Nadav<br><br>This patch addresses different issue from simplify-demanded-bits, where<br>condition in vselect is simplified regarding to BLEND* only takes the<br>highest bit. This patch address the issue regarding to the value being<br>selected not the selector. Says, V := select Cond, A, B. When A, or B or<br>both of them are all 0s or all 1s. We could exploit the fact that packed<br>comparison will generated all 0s or 1s in each SIMD lane. Such select<br>could be reduced to an AND/OR or simply removed.<br><br>Yours<br>- Michael<br><br><br><br>On Wed, 2013-04-10 at 17:30 -0700, Nadav Rotem wrote:<br><blockquote type="cite">Michael,<span class="Apple-converted-space"> </span><br><br><br>I think that the best way to handle the redundant sign-extending is to<br>improve the simplify-demanded-bits optimization. Last year I added<br>some code to optimize the X86::VSELECT using simplify-demanded-bits.<br>Do you know why it does not work ?<br><br><br>Thanks,<br>Nadav<br><br>On Apr 10, 2013, at 4:48 PM, Michael Liao <<a href="mailto:michael.liao@intel.com">michael.liao@intel.com</a>><br>wrote:<br><br><blockquote type="cite">Hi,<br><br>As we canonicalize sext from i1 to select in instcomb, it generates<br>redundant code to prepare all 0s and all 1s if we don't take it into<br>account that, in SSE/AVX, packed comparisons output all 0s or 1s in<br>SIMD lanes. The attached patch adds optimization for those cases and<br>transforms select into AND/OR to reduce BLEND pressure when<br>profitable.<br><br>Thanks for review<br>- Michael<br><br><0001-Add-optimization-to-leverage-all-0s-1s-produced-by-p.patch>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</blockquote></blockquote></div></blockquote></div><br></div></body></html>