<div dir="ltr">Hi Christian,<br><br>I'm seeing some test suite failures with this change on Linux x86_64:<br><br><span style="font-family:courier new,monospace">Failing Tests (7):<br> LLVM :: CodeGen/AArch64/func-calls.ll<br>
LLVM :: CodeGen/AArch64/sibling-call.ll<br> LLVM :: CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll<br> LLVM :: CodeGen/X86/avx-basic.ll<br> LLVM :: CodeGen/X86/avx-shuffle.ll<br> LLVM :: CodeGen/X86/lsr-loop-exit-cond.ll<br>
LLVM :: CodeGen/X86/shift-bmi2.ll</span><br></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Mar 20, 2013 at 9:49 AM, Christian Konig <span dir="ltr"><<a href="mailto:christian.koenig@amd.com" target="_blank">christian.koenig@amd.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ckoenig<br>
Date: Wed Mar 20 08:49:22 2013<br>
New Revision: 177518<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=177518&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=177518&view=rev</a><br>
Log:<br>
pre-RA-sched: fix TargetOpcode usage<br>
<br>
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.<br>
<br>
Signed-off-by: Christian König <<a href="mailto:christian.koenig@amd.com">christian.koenig@amd.com</a>><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=177518&r1=177517&r2=177518&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=177518&r1=177517&r2=177518&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Mar 20 08:49:22 2013<br>
@@ -1894,12 +1894,15 @@ unsigned RegReductionPQBase::getNodePrio<br>
// CopyToReg should be close to its uses to facilitate coalescing and<br>
// avoid spilling.<br>
return 0;<br>
- if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
- Opc == TargetOpcode::SUBREG_TO_REG ||<br>
- Opc == TargetOpcode::INSERT_SUBREG)<br>
- // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be<br>
- // close to their uses to facilitate coalescing.<br>
- return 0;<br>
+ if (SU->getNode() && SU->getNode()->isMachineOpcode()) {<br>
+ Opc = SU->getNode()->getMachineOpcode();<br>
+ if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
+ Opc == TargetOpcode::SUBREG_TO_REG ||<br>
+ Opc == TargetOpcode::INSERT_SUBREG)<br>
+ // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be<br>
+ // close to their uses to facilitate coalescing.<br>
+ return 0;<br>
+ }<br>
if (SU->NumSuccs == 0 && SU->NumPreds != 0)<br>
// If SU does not have a register use, i.e. it doesn't produce a value<br>
// that would be consumed (e.g. store), then it terminates a chain of<br>
@@ -2585,12 +2588,15 @@ static bool canEnableCoalescing(SUnit *S<br>
// avoid spilling.<br>
return true;<br>
<br>
- if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
- Opc == TargetOpcode::SUBREG_TO_REG ||<br>
- Opc == TargetOpcode::INSERT_SUBREG)<br>
- // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be<br>
- // close to their uses to facilitate coalescing.<br>
- return true;<br>
+ if (SU->getNode() && SU->getNode()->isMachineOpcode()) {<br>
+ Opc = SU->getNode()->getMachineOpcode();<br>
+ if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
+ Opc == TargetOpcode::SUBREG_TO_REG ||<br>
+ Opc == TargetOpcode::INSERT_SUBREG)<br>
+ // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be<br>
+ // close to their uses to facilitate coalescing.<br>
+ return true;<br>
+ }<br>
<br>
if (SU->NumPreds == 0 && SU->NumSuccs != 0)<br>
// If SU does not have a register def, schedule it close to its uses<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div>
</div>