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    <div class="moz-cite-prefix">I've reverted the commit for now.<br>
      <br>
      The code is trivial incorrect, but fixing it causes X86 to
      generate more inefficient code.<br>
      <br>
      Somebody with more knowledge of the code should take a look at it.<br>
      <br>
      Regards,<br>
      Christian.<br>
      <br>
      Am 20.03.2013 16:04, schrieb Koenig, Christian:<br>
    </div>
    <blockquote
      cite="mid:A4364598C2C10948901DA5A2C8D4BAC717443C@storexdag04.amd.com"
      type="cite">
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        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi
            Justin,<o:p></o:p></span></p>
        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Yeah,
            seeing that also. I usually don’t compile neither X86 nor
            AArch64 so I didn’t stumbled over it before committing (and
            the changes seemed trivial). Currently investigating into
            it.<o:p></o:p></span></p>
        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Christian.<o:p></o:p></span></p>
        <p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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              <p class="MsoNormal"><b><span
style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span
style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">
                  Justin Holewinski [<a class="moz-txt-link-freetext" href="mailto:justin.holewinski@gmail.com">mailto:justin.holewinski@gmail.com</a>]
                  <br>
                  <b>Sent:</b> Wednesday, March 20, 2013 3:47 PM<br>
                  <b>To:</b> Koenig, Christian<br>
                  <b>Cc:</b> llvm-commits<br>
                  <b>Subject:</b> Re: [llvm] r177518 - pre-RA-sched: fix
                  TargetOpcode usage<o:p></o:p></span></p>
            </div>
          </div>
          <p class="MsoNormal"><o:p> </o:p></p>
          <div>
            <p class="MsoNormal">Hi Christian,<br>
              <br>
              I'm seeing some test suite failures with this change on
              Linux x86_64:<br>
              <br>
              <span style="font-family:"Courier New"">Failing
                Tests (7):<br>
                    LLVM :: CodeGen/AArch64/func-calls.ll<br>
                    LLVM :: CodeGen/AArch64/sibling-call.ll<br>
                    LLVM ::
                CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll<br>
                    LLVM :: CodeGen/X86/avx-basic.ll<br>
                    LLVM :: CodeGen/X86/avx-shuffle.ll<br>
                    LLVM :: CodeGen/X86/lsr-loop-exit-cond.ll<br>
                    LLVM :: CodeGen/X86/shift-bmi2.ll</span><o:p></o:p></p>
          </div>
          <div>
            <p class="MsoNormal" style="margin-bottom:12.0pt"><o:p> </o:p></p>
            <div>
              <p class="MsoNormal">On Wed, Mar 20, 2013 at 9:49 AM,
                Christian Konig <<a moz-do-not-send="true"
                  href="mailto:christian.koenig@amd.com" target="_blank">christian.koenig@amd.com</a>>
                wrote:<o:p></o:p></p>
              <p class="MsoNormal">Author: ckoenig<br>
                Date: Wed Mar 20 08:49:22 2013<br>
                New Revision: 177518<br>
                <br>
                URL: <a moz-do-not-send="true"
                  href="http://llvm.org/viewvc/llvm-project?rev=177518&view=rev"
                  target="_blank">
http://llvm.org/viewvc/llvm-project?rev=177518&view=rev</a><br>
                Log:<br>
                pre-RA-sched: fix TargetOpcode usage<br>
                <br>
                TargetOpcodes need to be treaded as Machine- and not
                ISD-Opcodes.<br>
                <br>
                Signed-off-by: Christian König <<a
                  moz-do-not-send="true"
                  href="mailto:christian.koenig@amd..com">christian.koenig@amd.com</a>><br>
                <br>
                Modified:<br>
                   
                llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
                <br>
                Modified:
                llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp<br>
                URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=177518&r1=177517&r2=177518&view=diff"
                  target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=177518&r1=177517&r2=177518&view=diff</a><br>
==============================================================================<br>
                ---
                llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
                (original)<br>
                +++
                llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
                Wed Mar 20 08:49:22 2013<br>
                @@ -1894,12 +1894,15 @@ unsigned
                RegReductionPQBase::getNodePrio<br>
                     // CopyToReg should be close to its uses to
                facilitate coalescing and<br>
                     // avoid spilling.<br>
                     return 0;<br>
                -  if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
                -      Opc == TargetOpcode::SUBREG_TO_REG ||<br>
                -      Opc == TargetOpcode::INSERT_SUBREG)<br>
                -    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG
                nodes should be<br>
                -    // close to their uses to facilitate coalescing.<br>
                -    return 0;<br>
                +  if (SU->getNode() &&
                SU->getNode()->isMachineOpcode()) {<br>
                +    Opc = SU->getNode()->getMachineOpcode();<br>
                +    if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
                +        Opc == TargetOpcode::SUBREG_TO_REG ||<br>
                +        Opc == TargetOpcode::INSERT_SUBREG)<br>
                +      // EXTRACT_SUBREG, INSERT_SUBREG, and
                SUBREG_TO_REG nodes should be<br>
                +      // close to their uses to facilitate coalescing.<br>
                +      return 0;<br>
                +  }<br>
                   if (SU->NumSuccs == 0 && SU->NumPreds
                != 0)<br>
                     // If SU does not have a register use, i.e. it
                doesn't produce a value<br>
                     // that would be consumed (e.g. store), then it
                terminates a chain of<br>
                @@ -2585,12 +2588,15 @@ static bool
                canEnableCoalescing(SUnit *S<br>
                     // avoid spilling.<br>
                     return true;<br>
                <br>
                -  if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
                -      Opc == TargetOpcode::SUBREG_TO_REG ||<br>
                -      Opc == TargetOpcode::INSERT_SUBREG)<br>
                -    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG
                nodes should be<br>
                -    // close to their uses to facilitate coalescing.<br>
                -    return true;<br>
                +  if (SU->getNode() &&
                SU->getNode()->isMachineOpcode()) {<br>
                +    Opc = SU->getNode()->getMachineOpcode();<br>
                +    if (Opc == TargetOpcode::EXTRACT_SUBREG ||<br>
                +        Opc == TargetOpcode::SUBREG_TO_REG ||<br>
                +        Opc == TargetOpcode::INSERT_SUBREG)<br>
                +      // EXTRACT_SUBREG, INSERT_SUBREG, and
                SUBREG_TO_REG nodes should be<br>
                +      // close to their uses to facilitate coalescing.<br>
                +      return true;<br>
                +  }<br>
                <br>
                   if (SU->NumPreds == 0 && SU->NumSuccs
                != 0)<br>
                     // If SU does not have a register def, schedule it
                close to its uses<br>
                <br>
                <br>
                _______________________________________________<br>
                llvm-commits mailing list<br>
                <a moz-do-not-send="true"
                  href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
                <a moz-do-not-send="true"
                  href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits"
                  target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p>
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            <p class="MsoNormal" style="margin-bottom:12.0pt"><br>
              <br clear="all">
              <br>
              -- <o:p></o:p></p>
            <div>
              <p class="MsoNormal">Thanks,<o:p></o:p></p>
            </div>
            <div>
              <p class="MsoNormal"><o:p> </o:p></p>
            </div>
            <div>
              <p class="MsoNormal">Justin Holewinski<o:p></o:p></p>
            </div>
          </div>
        </div>
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      <pre wrap="">_______________________________________________
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</pre>
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