<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div></div><div><br></div><div>Thanks,</div><div>- Nadav</div><div><br></div><br><div><div>On Mar 14, 2013, at 12:09 AM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;">Author: ctopper<br>Date: Thu Mar 14 02:09:57 2013<br>New Revision: 177011<br><br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=177011&view=rev">http://llvm.org/viewvc/llvm-project?rev=177011&view=rev</a><br>Log:<br>Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.<br><br>Modified:<br> llvm/trunk/lib/Target/X86/X86MCInstLower.cpp<br><br>Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp<br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=177011&r1=177010&r2=177011&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=177011&r1=177010&r2=177011&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Thu Mar 14 02:09:57 2013<br>@@ -407,6 +407,48 @@ ReSimplify:<br> LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr<br> break;<br><br>+ // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B<br>+ // if one of the registers is extended, but other isn't.<br>+ case X86::VMOVAPDrr:<br>+ case X86::VMOVAPDYrr:<br>+ case X86::VMOVAPSrr:<br>+ case X86::VMOVAPSYrr:<br>+ case X86::VMOVDQArr:<br>+ case X86::VMOVDQAYrr:<br>+ case X86::VMOVDQUrr:<br>+ case X86::VMOVDQUYrr:<br>+ case X86::VMOVSDrr:<br>+ case X86::VMOVSSrr:<br>+ case X86::VMOVUPDrr:<br>+ case X86::VMOVUPDYrr:<br>+ case X86::VMOVUPSrr:<br>+ case X86::VMOVUPSYrr: {<br>+ if (X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&<br>+ !X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()))<br>+ break;<br>+<br>+ unsigned NewOpc;<br>+ switch (OutMI.getOpcode()) {<br>+ default: llvm_unreachable("Invalid opcode");<br>+ case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;<br>+ case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;<br>+ case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;<br>+ case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;<br>+ case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;<br>+ case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;<br>+ case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;<br>+ case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;<br>+ case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;<br>+ case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;<br>+ case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;<br>+ case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;<br>+ case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;<br>+ case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;<br>+ }<br>+ OutMI.setOpcode(NewOpc);<br>+ break;<br>+ }<br>+<br> // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register<br> // inputs modeled as normal uses instead of implicit uses. As such, truncate<br> // off all but the first operand (the callee). FIXME: Change isel.<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></body></html>