<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Muhammad, <div><br></div><div>The code looks good. Please update the cost model for this. Also, how did you verify the code ? I am asking because we don't have a good test coverage for vector code. </div><div><br></div><div>Thanks,</div><div>Nadav</div><div><br></div><div><br></div><div><div><div><div>On Mar 4, 2013, at 12:10 PM, Muhammad Tauqir Ahmad <<a href="mailto:muhammad.t.ahmad@intel.com">muhammad.t.ahmad@intel.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;">Optimize sext 4xi8 to 4xi64.<br><br>This produces nicer code for sext v4i8 -> v4i64 by generating vpmovsxbd instead of shift-left + shift-right pair.<br><br>Test included.<br><br><a href="http://llvm-reviews.chandlerc.com/D491">http://llvm-reviews.chandlerc.com/D491</a><br><br>Files:<br> lib/Target/X86/X86ISelLowering.cpp<br> test/CodeGen/X86/avx-sext.ll<br><br>Index: lib/Target/X86/X86ISelLowering.cpp<br>===================================================================<br>--- lib/Target/X86/X86ISelLowering.cpp<br>+++ lib/Target/X86/X86ISelLowering.cpp<br>@@ -11812,8 +11812,23 @@<br> // fall through<br> case MVT::v4i32:<br> case MVT::v8i16: {<br>- SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,<br>- Op.getOperand(0), ShAmt, DAG);<br>+ // (sext (vzext x)) -> (vsext x)<br>+ SDValue Op0 = Op.getOperand(0);<br>+ SDValue Op00 = Op0.getOperand(0);<br>+ SDValue Tmp1;<br>+ // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.<br>+ if (Op0.getOpcode() == ISD::BITCAST &&<br>+ Op00.getOpcode() == ISD::VECTOR_SHUFFLE)<br>+ Tmp1 = LowerVectorIntExtend(Op00, DAG);<br>+ if (Tmp1.getNode()) {<br>+ SDValue Tmp1Op0 = Tmp1.getOperand(0);<br>+ assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&<br>+ "This optimization is invalid without a VZEXT.");<br>+ return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));<br>+ }<br>+<br>+ // If the above didn't work, then just use Shift-Left + Shift-Right.<br>+ Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);<br> return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);<br> }<br> }<br>Index: test/CodeGen/X86/avx-sext.ll<br>===================================================================<br>--- test/CodeGen/X86/avx-sext.ll<br>+++ test/CodeGen/X86/avx-sext.ll<br>@@ -165,3 +165,13 @@<br> ret <4 x i64> %extmask<br>}<br><br>+; AVX: sext_4i8_to_4i64<br>+; AVX: vpmovsxbd<br>+; AVX: vpmovsxdq<br>+; AVX: vpmovsxdq<br>+; AVX: ret<br>+define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {<br>+ %X = load <4 x i8>* %ptr<br>+ %Y = sext <4 x i8> %X to <4 x i64><br>+ ret <4 x i64>%Y<br>+}<br><span><D491.1.patch></span>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></div></div></body></html>