<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div>Michael, </div><div><br></div><div>Thanks for the explanation. I think that the question that we need to ask ourselves is, does this belong in the compiler ? Before we design beautiful abstraction that will add to the complexity of the compiler we need to know if the complexity is worth it. <b> Michael, are you committed to doing __optimization__ work to support transactional memory </b>? If so, how will this work benefit others ? To my understanding, transactional memory is not something that is going to benefit many people. </div><div><br></div><div>Thanks,</div><div>Nadav</div><br><div><div>On Feb 20, 2013, at 5:34 PM, Michael Liao <<a href="mailto:michael.liao@intel.com">michael.liao@intel.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Hi Jeffery<br><br>Thanks for reminder. I will add documentation soon. So far, at IR level,<br>the only change is adding a metadata (!targetflags <N>) through the<br>patch. The flag word will be defined by target and not a generic one.<br><br>Target-specific flag should be helpful for other architectures, such as<br>Power. The similar HLE hint could be used by target backend to replace<br>regular atomic builtin with a HLE version if they have efficient TM<br>support.<br><br>Yours<br>- Michael<br><br>On Wed, 2013-02-20 at 17:28 -0800, Jeffrey Yasskin wrote:<br><blockquote type="cite">On Wed, Feb 20, 2013 at 5:08 PM, Chandler Carruth <<a href="mailto:chandlerc@google.com">chandlerc@google.com</a>> wrote:<br><blockquote type="cite">1) The base case: we must have a single spec for the LLVM IR model. This<br>should be tailored to the needs of optimizers, general enough to represent<br>the various builtins, and still support efficient lowering to both X86 and<br>potentially PPC implementations.<br></blockquote><br>Oh yeah, I'd forgotten this part. Michael, could you point us to your<br>patch against <a href="http://llvm.org/docs/Atomics.html">http://llvm.org/docs/Atomics.html</a> documenting your new<br>IR attributes? I didn't look through every patches, but I didn't see<br>any documentation in a brief scan.<br><br>Note that "Start a Hardware Lock Elision transaction with the atomic<br>operation." won't be sufficient, even if these are just<br>semantically-ignorable hints. I suspect that there's some<br>actually-useful semantics here that would make these operations usable<br>by other architectures if they ever add such instructions. For<br>example, see the documentation of the !nontemporal metadata.<br><br>Thanks,<br>Jeffrey<br></blockquote><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></div><br></body></html>