<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Bill, <div><br><div>Please, revert the change until a solution is found as this issue is blocking other testers.</div><div><br></div><div>Thanks,</div><div>Anna.<br><div><div>On Feb 20, 2013, at 2:52 PM, Anna Zaks <<a href="mailto:ganna@apple.com">ganna@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><meta http-equiv="Content-Type" content="text/html charset=us-ascii"><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">This is now failing on a public builder:<div><a href="http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/1755">http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/1755</a><div><br></div><div>Have you tried to repo this with Release+Asserts?</div><div><br></div><div>Please, let me know what exactly you'd like to see... </div><div><br></div><div><div>../build.clang-x86_64-darwin10-nobootstrap-RA/clang-build/Release+Asserts/bin/llc < ../build.clang-x86_64-darwin10-nobootstrap-RA/llvm/test/CodeGen/PowerPC/vec_constants.ll -march=ppc32 -mcpu=g5</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.machine ppc970</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.section<span class="Apple-tab-span" style="white-space:pre"> </span>__TEXT,__textcoal_nt,coalesced,pure_instructions</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.section<span class="Apple-tab-span" style="white-space:pre"> </span>__TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.section<span class="Apple-tab-span" style="white-space:pre"> </span>__TEXT,__text,regular,pure_instructions</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test1</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test1: ; @test1</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisb v2, -1</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mfspr r6, 256</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vslw v2, v2, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>oris r7, r6, 12288</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mtspr 256, r7</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>lvx v3, 0, r3</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vand v3, v3, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>stvx v3, 0, r3</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>lvx v3, 0, r4</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vandc v3, v3, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>stvx v3, 0, r4</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>lvx v3, 0, r5</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vandc v2, v3, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>stvx v2, 0, r5</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mtspr 256, r6</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_30</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_30: ; @test_30</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisw v2, 15</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vadduwm v2, v2, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_29</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_29: ; @test_29</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisw v2, -16</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisw v3, 13</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mfspr r3, 256</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vsubuwm v2, v3, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>oris r4, r3, 4096</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mtspr 256, r4</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mtspr 256, r3</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_n30</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_n30: ; @test_n30</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltish v2, -15</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vadduhm v2, v2, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_n104</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_n104: ; @test_n104</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisb v2, -13</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vslb v2, v2, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_vsldoi</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_vsldoi: ; @test_vsldoi</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisw v2, 2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vsldoi v2, v2, v2, 1</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_vsldoi_65023</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_vsldoi_65023: ; @test_vsldoi_65023</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltish v2, -3</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vsldoi v2, v2, v2, 1</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.globl<span class="Apple-tab-span" style="white-space:pre"> </span>_test_rol</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>.align<span class="Apple-tab-span" style="white-space:pre"> </span>4</div><div>_test_rol: ; @test_rol</div><div>; BB#0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vspltisw v2, -12</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>vrlw v2, v2, v2</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>blr </div><div><br></div><div>.subsections_via_symbols</div><div><br></div><div>smoosh-12:test buildslave$ </div></div><div><br></div><div>Anna.<br><div><div>On Feb 20, 2013, at 1:39 PM, Bill Schmidt <<a href="mailto:wschmidt@linux.vnet.ibm.com">wschmidt@linux.vnet.ibm.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">On Wed, 2013-02-20 at 13:21 -0800, Anna Zaks wrote:<br><blockquote type="cite">This commit introduced a failure in one of our internal bots.<br>(Possibly, the external ones haven't picked up this change yet.<br>Please, let me know if you need help reproducing the failure.)<br></blockquote><br>Hm. It would be helpful to see the assembly output produced on your<br>machine. This test is passing for me and I see that it passed for<br><a href="http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/2992">http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/2992</a>. This<br>seems to indicate that you are seeing an extra instruction interposed,<br>and I can't guess what that would be.<br><br>I just took the XFAIL off this test because it started working for me<br>when I restored these optimizations. From what I can tell, Ben<br>originally XFAIL'd it when the constant folding broke them. Ben, is<br>there anything else I need to do besides removing the XFAIL?<br><blockquote type="cite"><br></blockquote>Thanks,<br>Bill<br><blockquote type="cite"><br>Cheers,<br>Anna.<br>******************** TEST 'LLVM :: CodeGen/PowerPC/vec_constants.ll' FAILED ********************<br>Script:<br>--<br>../build.clang-x86_64-darwin10-nobootstrap-RA/clang-build/Release+Asserts/bin/llc < ../llvm/test/CodeGen/PowerPC/vec_constants.ll -march=ppc32 -mcpu=g5 | ../build.clang-x86_64-darwin10-nobootstrap-RA/clang-build/Release+Asserts/bin/FileCheck ../build.clang-x86_64-darwin10-nobootstrap-RA/llvm/test/CodeGen/PowerPC/vec_constants.ll<br>--<br>Exit Code: 1<br>Command Output (stderr):<br>--<br>../build.clang-x86_64-darwin10-nobootstrap-RA/llvm/test/CodeGen/PowerPC/vec_constants.ll:36:15: error: CHECK-NEXT: is not on the line after the previous match<br>; CHECK-NEXT: vsubuwm<br> ^<br><stdin>:41:2: note: 'next' match was here<br> vsubuwm v2, v3, v2<br> ^<br><stdin>:39:10: note: previous match was here<br> vspltisw v3, 13<br> ^<br>--<br><br><br>On Feb 20, 2013, at 12:41 PM, Bill Schmidt<br><<a href="mailto:wschmidt@linux.vnet.ibm.com">wschmidt@linux.vnet.ibm.com</a>> wrote:<br><br><blockquote type="cite">Author: wschmidt<br>Date: Wed Feb 20 14:41:42 2013<br>New Revision: 175663<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=175663&view=rev">http://llvm.org/viewvc/llvm-project?rev=175663&view=rev</a><br>Log:<br>Additional fixes for bug 15155.<br><br>This handles the cases where the 6-bit splat element is odd,<br>converting<br>to a three-instruction sequence to add or subtract two splats. With<br>this<br>fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed.<br><br>Modified:<br> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br> llvm/trunk/test/CodeGen/PowerPC/vaddsplat.ll<br> llvm/trunk/test/CodeGen/PowerPC/vec_constants.ll<br><br>Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=175663&r1=175662&r2=175663&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=175663&r1=175662&r2=175663&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)<br>+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Feb 20<br>14:41:42 2013<br>@@ -1323,34 +1323,75 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *<br> SDValue(Tmp, 0), GA);<br> }<br> case PPCISD::VADD_SPLAT: {<br>- // Convert: VADD_SPLAT elt, size<br>- // Into: tmp = VSPLTIS[BHW] elt<br>- // VADDU[BHW]M tmp, tmp<br>- // Where: [BHW] = B for size = 1, H for size = 2, W for size<br>= 4<br>+ // This expands into one of three sequences, depending on<br>whether<br>+ // the first operand is odd or even, positive or negative.<br> assert(isa<ConstantSDNode>(N->getOperand(0)) &&<br> isa<ConstantSDNode>(N->getOperand(1)) &&<br> "Invalid operand on VADD_SPLAT!");<br>+<br>+ int Elt = N->getConstantOperandVal(0);<br> int EltSize = N->getConstantOperandVal(1);<br>- unsigned Opc1, Opc2;<br>+ unsigned Opc1, Opc2, Opc3;<br> EVT VT;<br>+<br> if (EltSize == 1) {<br> Opc1 = PPC::VSPLTISB;<br> Opc2 = PPC::VADDUBM;<br>+ Opc3 = PPC::VSUBUBM;<br> VT = MVT::v16i8;<br> } else if (EltSize == 2) {<br> Opc1 = PPC::VSPLTISH;<br> Opc2 = PPC::VADDUHM;<br>+ Opc3 = PPC::VSUBUHM;<br> VT = MVT::v8i16;<br> } else {<br> assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");<br> Opc1 = PPC::VSPLTISW;<br> Opc2 = PPC::VADDUWM;<br>+ Opc3 = PPC::VSUBUWM;<br> VT = MVT::v4i32;<br> }<br>- SDValue Elt = getI32Imm(N->getConstantOperandVal(0));<br>- SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, Elt);<br>- SDValue TmpVal = SDValue(Tmp, 0);<br>- return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);<br>+<br>+ if ((Elt & 1) == 0) {<br>+ // Elt is even, in the range [-32,-18] + [16,30].<br>+ //<br>+ // Convert: VADD_SPLAT elt, size<br>+ // Into: tmp = VSPLTIS[BHW] elt<br>+ // VADDU[BHW]M tmp, tmp<br>+ // Where: [BHW] = B for size = 1, H for size = 2, W for<br>size = 4<br>+ SDValue EltVal = getI32Imm(Elt >> 1);<br>+ SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);<br>+ SDValue TmpVal = SDValue(Tmp, 0);<br>+ return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);<br>+<br>+ } else if (Elt > 0) {<br>+ // Elt is odd and positive, in the range [17,31].<br>+ //<br>+ // Convert: VADD_SPLAT elt, size<br>+ // Into: tmp1 = VSPLTIS[BHW] elt-16<br>+ // tmp2 = VSPLTIS[BHW] -16<br>+ // VSUBU[BHW]M tmp1, tmp2<br>+ SDValue EltVal = getI32Imm(Elt - 16);<br>+ SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);<br>+ EltVal = getI32Imm(-16);<br>+ SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);<br>+ return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),<br>+ SDValue(Tmp2, 0));<br>+<br>+ } else {<br>+ // Elt is odd and negative, in the range [-31,-17].<br>+ //<br>+ // Convert: VADD_SPLAT elt, size<br>+ // Into: tmp1 = VSPLTIS[BHW] elt+16<br>+ // tmp2 = VSPLTIS[BHW] -16<br>+ // VADDU[BHW]M tmp1, tmp2<br>+ SDValue EltVal = getI32Imm(Elt + 16);<br>+ SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);<br>+ EltVal = getI32Imm(-16);<br>+ SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);<br>+ return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),<br>+ SDValue(Tmp2, 0));<br>+ }<br> }<br> }<br><br><br>Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=175663&r1=175662&r2=175663&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=175663&r1=175662&r2=175663&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 20<br>14:41:42 2013<br>@@ -5025,11 +5025,17 @@ SDValue PPCTargetLowering::LowerBUILD_VE<br> // Two instruction sequences.<br><br> // If this value is in the range [-32,30] and is even, use:<br>- // tmp = VSPLTI[bhw], result = add tmp, tmp<br>- if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {<br>- // To avoid having the optimization undone by constant folding,<br>we<br>- // convert to a pseudo that will be expanded later.<br>- SDValue Elt = DAG.getConstant(SextVal >> 1, MVT::i32);<br>+ // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)<br>+ // If this value is in the range [17,31] and is odd, use:<br>+ // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)<br>+ // If this value is in the range [-31,-17] and is odd, use:<br>+ // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)<br>+ // Note the last two are three-instruction sequences.<br>+ if (SextVal >= -32 && SextVal <= 31) {<br>+ // To avoid having these optimizations undone by constant<br>folding,<br>+ // we convert to a pseudo that will be expanded later into one<br>of<br>+ // the above forms.<br>+ SDValue Elt = DAG.getConstant(SextVal, MVT::i32);<br> EVT VT = Op.getValueType();<br> int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);<br> SDValue EltSize = DAG.getConstant(Size, MVT::i32);<br>@@ -5129,25 +5135,6 @@ SDValue PPCTargetLowering::LowerBUILD_VE<br> }<br> }<br><br>- // Three instruction sequences.<br>-<br>- // Odd, in range [17,31]: (vsplti C)-(vsplti -16).<br>- // FIXME: Disabled because the add gets constant folded.<br>- if (0 && SextVal >= 0 && SextVal <= 31) {<br>- SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other,<br>DAG, dl);<br>- SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);<br>- LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);<br>- return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);<br>- }<br>- // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).<br>- // FIXME: Disabled because the add gets constant folded.<br>- if (0 && SextVal >= -31 && SextVal <= 0) {<br>- SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other,<br>DAG, dl);<br>- SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);<br>- LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);<br>- return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);<br>- }<br>-<br> return SDValue();<br>}<br><br><br>Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>URL:<br>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=175663&r1=175662&r2=175663&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)<br>+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Feb 20<br>14:41:42 2013<br>@@ -238,8 +238,9 @@ namespace llvm {<br> ADDI_DTPREL_L,<br><br> /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be<br>expanded<br>- /// into an ADD of a VSPLTI with itself during instruction<br>selection.<br>- /// Necessary to avoid losing this optimization due to<br>constant folds.<br>+ /// during instruction selection to optimize a BUILD_VECTOR<br>into<br>+ /// operations on splats. This is necessary to avoid losing<br>these<br>+ /// optimizations due to constant folding.<br> VADD_SPLAT,<br><br> /// STD_32 - This is the STD instruction for use with "32-bit"<br>registers.<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/vaddsplat.ll<br>URL:<br>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vaddsplat.ll?rev=175663&r1=175662&r2=175663&view=diff<br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/vaddsplat.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/vaddsplat.ll Wed Feb 20 14:41:42<br>2013<br>@@ -1,6 +1,6 @@<br>; RUN: llc -O0 -mcpu=pwr7 <%s | FileCheck %s<br><br>-; Test optimization of build_vector into vadd/vsplt for 6-bit<br>immediates.<br>+; Test optimizations of build_vector for 6-bit immediates.<br><br>target datalayout =<br>"E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"<br>target triple = "powerpc64-unknown-linux-gnu"<br>@@ -9,69 +9,141 @@ target triple = "powerpc64-unknown-linux<br>%v8i16 = type <8 x i16><br>%v16i8 = type <16 x i8><br><br>-define void @test_v4i32_pos(%v4i32* %P, %v4i32* %S) {<br>+define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {<br> %p = load %v4i32* %P<br> %r = add %v4i32 %p, < i32 18, i32 18, i32 18, i32 18 ><br> store %v4i32 %r, %v4i32* %S<br> ret void<br>}<br><br>-; CHECK: test_v4i32_pos:<br>+; CHECK: test_v4i32_pos_even:<br>; CHECK: vspltisw [[REG1:[0-9]+]], 9<br>; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>-define void @test_v4i32_neg(%v4i32* %P, %v4i32* %S) {<br>+define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {<br> %p = load %v4i32* %P<br> %r = add %v4i32 %p, < i32 -28, i32 -28, i32 -28, i32 -28 ><br> store %v4i32 %r, %v4i32* %S<br> ret void<br>}<br><br>-; CHECK: test_v4i32_neg:<br>+; CHECK: test_v4i32_neg_even:<br>; CHECK: vspltisw [[REG1:[0-9]+]], -14<br>; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>-define void @test_v8i16_pos(%v8i16* %P, %v8i16* %S) {<br>+define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {<br> %p = load %v8i16* %P<br> %r = add %v8i16 %p, < i16 30, i16 30, i16 30, i16 30, i16 30,<br>i16 30, i16 30, i16 30 ><br> store %v8i16 %r, %v8i16* %S<br> ret void<br>}<br><br>-; CHECK: test_v8i16_pos:<br>+; CHECK: test_v8i16_pos_even:<br>; CHECK: vspltish [[REG1:[0-9]+]], 15<br>; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>-define void @test_v8i16_neg(%v8i16* %P, %v8i16* %S) {<br>+define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {<br> %p = load %v8i16* %P<br> %r = add %v8i16 %p, < i16 -32, i16 -32, i16 -32, i16 -32, i16<br>-32, i16 -32, i16 -32, i16 -32 ><br> store %v8i16 %r, %v8i16* %S<br> ret void<br>}<br><br>-; CHECK: test_v8i16_neg:<br>+; CHECK: test_v8i16_neg_even:<br>; CHECK: vspltish [[REG1:[0-9]+]], -16<br>; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>-define void @test_v16i8_pos(%v16i8* %P, %v16i8* %S) {<br>+define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {<br> %p = load %v16i8* %P<br> %r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8<br>16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16,<br>i8 16 ><br> store %v16i8 %r, %v16i8* %S<br> ret void<br>}<br><br>-; CHECK: test_v16i8_pos:<br>+; CHECK: test_v16i8_pos_even:<br>; CHECK: vspltisb [[REG1:[0-9]+]], 8<br>; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>-define void @test_v16i8_neg(%v16i8* %P, %v16i8* %S) {<br>+define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {<br> %p = load %v16i8* %P<br> %r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18,<br>i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8<br>-18, i8 -18, i8 -18 ><br> store %v16i8 %r, %v16i8* %S<br> ret void<br>}<br><br>-; CHECK: test_v16i8_neg:<br>+; CHECK: test_v16i8_neg_even:<br>; CHECK: vspltisb [[REG1:[0-9]+]], -9<br>; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]<br><br>+define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {<br>+ %p = load %v4i32* %P<br>+ %r = add %v4i32 %p, < i32 27, i32 27, i32 27, i32 27 ><br>+ store %v4i32 %r, %v4i32* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v4i32_pos_odd:<br>+; CHECK: vspltisw [[REG2:[0-9]+]], -16<br>+; CHECK: vspltisw [[REG1:[0-9]+]], 11<br>+; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br>+define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {<br>+ %p = load %v4i32* %P<br>+ %r = add %v4i32 %p, < i32 -27, i32 -27, i32 -27, i32 -27 ><br>+ store %v4i32 %r, %v4i32* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v4i32_neg_odd:<br>+; CHECK: vspltisw [[REG2:[0-9]+]], -16<br>+; CHECK: vspltisw [[REG1:[0-9]+]], -11<br>+; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br>+define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {<br>+ %p = load %v8i16* %P<br>+ %r = add %v8i16 %p, < i16 31, i16 31, i16 31, i16 31, i16<br>31, i16 31, i16 31, i16 31 ><br>+ store %v8i16 %r, %v8i16* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v8i16_pos_odd:<br>+; CHECK: vspltish [[REG2:[0-9]+]], -16<br>+; CHECK: vspltish [[REG1:[0-9]+]], 15<br>+; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br>+define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {<br>+ %p = load %v8i16* %P<br>+ %r = add %v8i16 %p, < i16 -31, i16 -31, i16 -31, i16 -31,<br>i16 -31, i16 -31, i16 -31, i16 -31 ><br>+ store %v8i16 %r, %v8i16* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v8i16_neg_odd:<br>+; CHECK: vspltish [[REG2:[0-9]+]], -16<br>+; CHECK: vspltish [[REG1:[0-9]+]], -15<br>+; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br>+define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {<br>+ %p = load %v16i8* %P<br>+ %r = add %v16i8 %p, < i8 17, i8 17, i8 17, i8 17, i8 17, i8<br>17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17,<br>i8 17 ><br>+ store %v16i8 %r, %v16i8* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v16i8_pos_odd:<br>+; CHECK: vspltisb [[REG2:[0-9]+]], -16<br>+; CHECK: vspltisb [[REG1:[0-9]+]], 1<br>+; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br>+define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) {<br>+ %p = load %v16i8* %P<br>+ %r = add %v16i8 %p, < i8 -17, i8 -17, i8 -17, i8 -17, i8<br>-17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17,<br>i8 -17, i8 -17, i8 -17 ><br>+ store %v16i8 %r, %v16i8* %S<br>+ ret void<br>+}<br>+<br>+; CHECK: test_v16i8_neg_odd:<br>+; CHECK: vspltisb [[REG2:[0-9]+]], -16<br>+; CHECK: vspltisb [[REG1:[0-9]+]], -1<br>+; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]<br>+<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/vec_constants.ll<br>URL:<br>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_constants.ll?rev=175663&r1=175662&r2=175663&view=diff<br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/vec_constants.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/vec_constants.ll Wed Feb 20<br>14:41:42 2013<br>@@ -1,5 +1,4 @@<br>; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s<br>-; XFAIL: *<br><br>define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3)<br>nounwind {<br>%tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]<br><br><br>_______________________________________________<br>llvm-commits mailing list<br>llvm-commits@cs.uiuc.edu<br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote><br><br></blockquote><br></blockquote></div><br></div></div></div>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></div><br></div></div></body></html>