<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Feb 19, 2013 at 10:46 PM, Cameron Zwarich <span dir="ltr"><<a href="mailto:zwarich@apple.com" target="_blank">zwarich@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: zwarich<br>
Date: Wed Feb 20 00:46:48 2013<br>
New Revision: 175604<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=175604&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=175604&view=rev</a><br>
Log:<br>
Add support to the two-address pass for updating LiveIntervals in many of the<br>
common transformations. This includes updating repairIntervalsInRange() to<br>
handle more cases.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br>
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=175604&r1=175603&r2=175604&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=175604&r1=175603&r2=175604&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Feb 20 00:46:48 2013<br>
@@ -1038,20 +1038,36 @@ LiveIntervals::repairIntervalsInRange(Ma<br>
MachineBasicBlock::iterator Begin,<br>
MachineBasicBlock::iterator End,<br>
ArrayRef<unsigned> OrigRegs) {<br>
- SlotIndex startIdx;<br>
- if (Begin == MBB->begin())<br>
- startIdx = getMBBStartIdx(MBB);<br>
+ SlotIndex endIdx;<br>
+ if (End == MBB->end())<br>
+ endIdx = getMBBEndIdx(MBB).getPrevSlot();<br>
else<br>
- startIdx = getInstructionIndex(prior(Begin)).getRegSlot();<br>
+ endIdx = getInstructionIndex(End);<br>
<br>
Indexes->repairIndexesInRange(MBB, Begin, End);<br>
<br>
+ for (MachineBasicBlock::iterator I = End; I != Begin;) {<br>
+ --I;<br>
+ MachineInstr *MI = I;<br>
+ for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),<br>
+ MOE = MI->operands_end(); MOI != MOE; ++MOI) {<br>
+ if (MOI->isReg() &&<br>
+ TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&<br>
+ !hasInterval(MOI->getReg())) {<br>
+ LiveInterval &LI = getOrCreateInterval(MOI->getReg());<br>
+ computeVirtRegInterval(&LI);<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {<br>
unsigned Reg = OrigRegs[i];<br>
if (!TargetRegisterInfo::isVirtualRegister(Reg))<br>
continue;<br>
<br>
LiveInterval &LI = getInterval(Reg);<br>
+ LiveInterval::iterator LII = LI.FindLiveRangeContaining(endIdx);<br>
+<br>
for (MachineBasicBlock::iterator I = End; I != Begin;) {<br>
--I;<br>
MachineInstr *MI = I;<br>
@@ -1063,13 +1079,26 @@ LiveIntervals::repairIntervalsInRange(Ma<br>
if (!MO.isReg() || MO.getReg() != Reg)<br>
continue;<br>
<br>
- assert(MO.isUse() && "Register defs are not yet supported.");<br>
-<br>
- if (!LI.liveAt(instrIdx)) {<br>
- LiveRange *LR = LI.getLiveRangeContaining(startIdx);<br>
- assert(LR && "Used registers must be live-in.");<br>
- LR->end = instrIdx.getRegSlot();<br>
- break;<br>
+ if (MO.isDef()) {<br>
+ assert(LII != LI.end() &&<br>
+ "Dead register defs are not yet supported.");<br>
+ if (!Indexes->getInstructionFromIndex(LII->start)) {<br>
+ LII->start = instrIdx.getRegSlot();<br>
+ LII->valno->def = instrIdx.getRegSlot();<br>
+ } else if (LII->start != instrIdx.getRegSlot()) {<br>
+ VNInfo *VNI = LI.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);<br>
+ LiveRange LR = LiveRange(instrIdx.getRegSlot(), LII->start, VNI);<br>
+ LII = LI.addRange(LR);<br>
+ }<br>
+ } else if (MO.isUse()) {<br>
+ if (LII == LI.end())<br>
+ --LII;<br>
+<br>
+ assert(LII->start < instrIdx &&<br>
+ "Registers with multiple used live ranges are not yet supported.");<br>
+ SlotIndex endIdx = LII->end;<br>
+ if (!endIdx.isBlock() && !Indexes->getInstructionFromIndex(endIdx))<br>
+ LII->end = instrIdx.getRegSlot();<br>
}<br>
}<br>
}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=175604&r1=175603&r2=175604&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=175604&r1=175603&r2=175604&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Feb 20 00:46:48 2013<br>
@@ -1149,7 +1149,29 @@ tryInstructionTransform(MachineBasicBloc<br>
}<br>
LV->addVirtualRegisterKilled(Reg, NewMIs[1]);<br>
}<br>
+<br>
+ MachineBasicBlock::iterator Begin;<br>
+ MachineBasicBlock::iterator End;<br>
+ SmallVector<unsigned, 4> OrigRegs;<br>
+ if (LIS) {<br>
+ Begin = MachineBasicBlock::iterator(NewMIs[0]);<br>
+ if (Begin != MBB->begin())<br>
+ --Begin;<br>
+ End = next(MachineBasicBlock::iterator(MI));<br></blockquote><div><br></div><div>This</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+<br>
+ for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),<br>
+ MOE = MI.operands_end(); MOI != MOE; ++MOI) {<br>
+ if (MOI->isReg())<br>
+ OrigRegs.push_back(MOI->getReg());<br>
+ }<br>
+ }<br>
+<br>
MI.eraseFromParent();<br>
+<br>
+ // Update LiveIntervals.<br>
+ if (LIS)<br>
+ LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);<br>
+<br>
mi = NewMIs[1];<br>
if (TransformSuccess)<br>
return true;<br>
@@ -1223,6 +1245,7 @@ TwoAddressInstructionPass::processTiedPa<br>
bool RemovedKillFlag = false;<br>
bool AllUsesCopied = true;<br>
unsigned LastCopiedReg = 0;<br>
+ SlotIndex LastCopyIdx;<br>
unsigned RegB = 0;<br>
for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {<br>
unsigned SrcIdx = TiedPairs[tpi].first;<br>
@@ -1267,9 +1290,17 @@ TwoAddressInstructionPass::processTiedPa<br>
DistanceMap.insert(std::make_pair(PrevMI, Dist));<br>
DistanceMap[MI] = ++Dist;<br>
<br>
- SlotIndex CopyIdx;<br>
- if (Indexes)<br>
- CopyIdx = Indexes->insertMachineInstrInMaps(PrevMI).getRegSlot();<br>
+ if (LIS) {<br>
+ LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();<br>
+<br>
+ if (TargetRegisterInfo::isVirtualRegister(RegA)) {<br>
+ LiveInterval &LI = LIS->getInterval(RegA);<br>
+ VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());<br>
+ SlotIndex endIdx =<br>
+ LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);<br>
+ LI.addRange(LiveRange(LastCopyIdx, endIdx, VNI));<br>
+ }<br>
+ }<br>
<br>
DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);<br>
<br>
@@ -1315,6 +1346,18 @@ TwoAddressInstructionPass::processTiedPa<br>
LV->addVirtualRegisterKilled(RegB, PrevMI);<br>
}<br>
<br>
+ // Update LiveIntervals.<br>
+ if (LIS) {<br>
+ LiveInterval &LI = LIS->getInterval(RegB);<br>
+ SlotIndex MIIdx = LIS->getInstructionIndex(MI);<br>
+ LiveInterval::const_iterator I = LI.find(MIIdx);<br>
+ assert(I != LI.end() && "RegB must be live-in to use.");<br>
+<br>
+ SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);<br>
+ if (I->end == UseIdx)<br>
+ LI.removeRange(LastCopyIdx, UseIdx);<br>
+ }<br>
+<br>
} else if (RemovedKillFlag) {<br>
// Some tied uses of regB matched their destination registers, so<br>
// regB is still used in this instruction, but a kill flag was<br>
@@ -1469,6 +1512,13 @@ eliminateRegSequence(MachineBasicBlock::<br>
llvm_unreachable(0);<br>
}<br>
<br>
+ SmallVector<unsigned, 4> OrigRegs;<br>
+ if (LIS) {<br>
+ OrigRegs.push_back(MI->getOperand(0).getReg());<br>
+ for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)<br>
+ OrigRegs.push_back(MI->getOperand(i).getReg());<br>
+ }<br>
+<br>
bool DefEmitted = false;<br>
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {<br>
MachineOperand &UseMO = MI->getOperand(i);<br>
@@ -1512,6 +1562,8 @@ eliminateRegSequence(MachineBasicBlock::<br>
DEBUG(dbgs() << "Inserted: " << *CopyMI);<br>
}<br>
<br>
+ MachineBasicBlock::iterator EndMBBI = next(MachineBasicBlock::iterator(MI));<br></blockquote><div><br></div><div>And this call to 'next' are ambiguous in C++11. I've qualified them to llvm::next in r175608 to unbreak the C++11 build.</div>
<div><br></div><div style>- David</div>
<div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+<br>
if (!DefEmitted) {<br>
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");<br>
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));<br>
@@ -1521,4 +1573,11 @@ eliminateRegSequence(MachineBasicBlock::<br>
DEBUG(dbgs() << "Eliminated: " << *MI);<br>
MI->eraseFromParent();<br>
}<br>
+<br>
+ // Udpate LiveIntervals.<br>
+ if (LIS) {<br>
+ if (MBBI != MBB->begin())<br>
+ --MBBI;<br>
+ LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);<br>
+ }<br>
}<br>
<br>
<br>
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</blockquote></div><br></div></div>