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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>Hi,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>It seems there is a bug in optimization arm_ldst_opt, so I filed an entry at <a href="http://llvm.org/bugs/show_bug.cgi?id=14824">http://llvm.org/bugs/show_bug.cgi?id=14824</a>. Can anybody confirm this issue?<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>Thanks,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>-Jiangning<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>=================================<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>Optimization arm_ldst_opt inserts newly generated instruction vldmia at<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>incorrect position.<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>For attached small test case ldst_opt_bug.ll, using this command line,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>llc -mcpu=cortex-a9 -mattr=+neon,+neonfp ldst_opt_bug.ll<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>we would see incorrect instruction sequence in ldst_opt_bug.s like below,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldr s0, [r0, #432]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldr s5, [r1, #412]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldr s14, [r1, #440]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldr s10, [r0, #440]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldmia r3, {s0, s1, s2, s3}<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> add.w r3, r2, #432<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> vldr s7, [r1, #420]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>That is, instruction "vldmia r3, {s0, s1, s2, s3}" overwrites s0 just loaded<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>by "vldr s0, [r0, #432]", which is incorrect according to the original LLVM<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>IR semantics in ldst_opt_bug.ll.<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>In optimization arm_ldst_opt, before generating instruction vldmia, we have the<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>following IR,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(1) %S0<def> = VLDRS %R0, 102, pred:14, pred:%noreg, %Q0<imp-def>;<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>mem:LD4[%arrayidx67+24](align=8)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(2) %S1<def> = VLDRS %R0, 103, pred:14, pred:%noreg, %Q0<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q0<imp-def>; mem:LD4[%arrayidx67+28]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(3) %S11<def> = VLDRS %R0, 111, pred:14, pred:%noreg, %Q2<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q2<imp-def>; mem:LD4[%arrayidx67+60]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(4) %S10<def> = VLDRS %R0, 110, pred:14, pred:%noreg, %Q2<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q2<imp-def>; mem:LD4[%arrayidx67+56](align=8)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(5) %S1<def> = VLDRS %R0, 109, pred:14, pred:%noreg, %Q0<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q0<imp-def>; mem:LD4[%arrayidx67+52]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(6) %S0<def> = VLDRS %R0, 108, pred:14, pred:%noreg, %Q0<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q0<imp-def>; mem:LD4[%arrayidx67+48](align=16)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(7) %S3<def> = VLDRS %R0, 105, pred:14, pred:%noreg, %Q0<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q0<imp-def>; mem:LD4[%arrayidx67+36]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(8) %S2<def> = VLDRS %R0, 104, pred:14, pred:%noreg, %Q0<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q0<imp-def>; mem:LD4[%arrayidx67+32](align=32)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(9) %S7<def> = VLDRS %R1, 105, pred:14, pred:%noreg, %Q1<imp-use,kill>,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>%Q1<imp-def>; mem:LD4[%arrayidx64+36]<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>The optimization tries to hoist instruction 7) and 8) to be able to merge with<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>1) and 2) to generate vldm, because they are loading sequential memory at<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>offset 102*4, 103*4, 104*4, 105*4. This intention of the optimization itself is<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>correct.<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>After hoist, the algorithm firstly generates an internal instruction sequence,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(1)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(2)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(7)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>(8)<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>The problem is the newly generated instruction vldm is incorrectly inserted<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>after instruction 8). Obviously the data dependence is violated here with<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>instruction 6).<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>The source code introducing the bug has something to do with the function<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>ARMLoadStoreOpt::MergeOpsUpdate,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> // Try to do the merge.<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> MachineBasicBlock::iterator Loc = memOps[insertAfter].MBBI;<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> ++Loc;<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> Pred, PredReg, Scratch, dl, Regs, ImpDefs))<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'> return;<o:p></o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>When Loc is (8), ++Loc is (9).<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Courier New"'><o:p> </o:p></span></p></div></body></html>