Sorry about that. I've fixed and recommitted in r171356.<br><br><div class="gmail_quote">On Tue, Jan 1, 2013 at 5:37 PM, Rafael Espíndola <span dir="ltr"><<a href="mailto:rafael.espindola@gmail.com" target="_blank">rafael.espindola@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I reverted this as it had broken MC/X86/x86-32-avx.s.<br>
<br>
On 1 January 2013 15:53, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:<br>
> Author: ctopper<br>
> Date: Tue Jan 1 14:53:20 2013<br>
> New Revision: 171351<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=171351&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=171351&view=rev</a><br>
> Log:<br>
> Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=171351&r1=171350&r2=171351&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=171351&r1=171350&r2=171351&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jan 1 14:53:20 2013<br>
> @@ -2936,6 +2936,26 @@<br>
> /// sse1_fp_unop_s - SSE1 unops in scalar form.<br>
> multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,<br>
> SDNode OpNode, Intrinsic F32Int, OpndItins itins> {<br>
> +let Predicates = [HasAVX], hasSideEffects = 0 in {<br>
> + def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),<br>
> + (ins FR32:$src1, FR32:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + let mayLoad = 1 in {<br>
> + def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),<br>
> + (ins FR32:$src1,f32mem:$src2),<br>
> + !strconcat(OpcodeStr,<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> + (ins VR128:$src1, ssmem:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + }<br>
> +}<br>
> +<br>
> def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),<br>
> !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),<br>
> [(set FR32:$dst, (OpNode FR32:$src))]>;<br>
> @@ -2955,19 +2975,50 @@<br>
> [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;<br>
> }<br>
><br>
> -/// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.<br>
> -multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {<br>
> - def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> +/// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.<br>
> +multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
> + OpndItins itins> {<br>
> +let Predicates = [HasAVX], hasSideEffects = 0 in {<br>
> + def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),<br>
> + (ins FR32:$src1, FR32:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> let mayLoad = 1 in {<br>
> - def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> - def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> - (ins VR128:$src1, ssmem:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> + def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),<br>
> + (ins FR32:$src1,f32mem:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> + (ins VR128:$src1, ssmem:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + }<br>
> +}<br>
> +<br>
> + def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),<br>
> + !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),<br>
> + [(set FR32:$dst, (OpNode FR32:$src))]>;<br>
> + // For scalar unary operations, fold a load into the operation<br>
> + // only in OptForSize mode. It eliminates an instruction, but it also<br>
> + // eliminates a whole-register clobber (the load), so it introduces a<br>
> + // partial register update condition.<br>
> + def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),<br>
> + !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),<br>
> + [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,<br>
> + Requires<[UseSSE1, OptForSize]>;<br>
> + let Constraints = "$src1 = $dst" in {<br>
> + def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),<br>
> + (ins VR128:$src1, VR128:$src2),<br>
> + !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),<br>
> + [], itins.rr>;<br>
> + let mayLoad = 1, hasSideEffects = 0 in<br>
> + def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> + (ins VR128:$src1, ssmem:$src2),<br>
> + !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),<br>
> + [], itins.rm>;<br>
> }<br>
> }<br>
><br>
> @@ -3046,6 +3097,26 @@<br>
> /// sse2_fp_unop_s - SSE2 unops in scalar form.<br>
> multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,<br>
> SDNode OpNode, Intrinsic F64Int, OpndItins itins> {<br>
> +let Predicates = [HasAVX], hasSideEffects = 0 in {<br>
> + def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),<br>
> + (ins FR64:$src1, FR64:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + let mayLoad = 1 in {<br>
> + def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),<br>
> + (ins FR64:$src1,f64mem:$src2),<br>
> + !strconcat(OpcodeStr,<br>
> + "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> + (ins VR128:$src1, sdmem:$src2),<br>
> + !strconcat(!strconcat("v", OpcodeStr),<br>
> + "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + []>, VEX_4V, VEX_LIG;<br>
> + }<br>
> +}<br>
> +<br>
> def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),<br>
> !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),<br>
> [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;<br>
> @@ -3062,24 +3133,7 @@<br>
> [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;<br>
> }<br>
><br>
> -/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.<br>
> -let hasSideEffects = 0 in<br>
> -multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {<br>
> - def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> - let mayLoad = 1 in {<br>
> - def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> - def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> - (ins VR128:$src1, sdmem:$src2),<br>
> - !strconcat(OpcodeStr,<br>
> - "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;<br>
> - }<br>
> -}<br>
> -<br>
> -/// sse2_fp_unop_p_new - SSE2 unops in vector forms.<br>
> +/// sse2_fp_unop_p - SSE2 unops in vector forms.<br>
> multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,<br>
> SDNode OpNode, OpndItins itins> {<br>
> let Predicates = [HasAVX] in {<br>
> @@ -3113,26 +3167,25 @@<br>
> [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;<br>
> }<br>
><br>
> -defm SQRT : sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,<br>
> +// Square root.<br>
> +defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,<br>
> + SSE_SQRTS>,<br>
> + sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,<br>
> + sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,<br>
> + SSE_SQRTS>,<br>
> sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;<br>
> -defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,<br>
> +<br>
> +// Reciprocal approximations. Note that these typically require refinement<br>
> +// in order to obtain suitable precision.<br>
> +defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,<br>
> + sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,<br>
> sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,<br>
> int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;<br>
> -defm RCP : sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,<br>
> +defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,<br>
> + sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,<br>
> sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,<br>
> int_x86_avx_rcp_ps_256, SSE_RCPP>;<br>
><br>
> -let Predicates = [HasAVX] in {<br>
> - // Square root.<br>
> - defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,<br>
> - sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;<br>
> -<br>
> - // Reciprocal approximations. Note that these typically require refinement<br>
> - // in order to obtain suitable precision.<br>
> - defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;<br>
> - defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;<br>
> -}<br>
> -<br>
> def : Pat<(f32 (fsqrt FR32:$src)),<br>
> (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;<br>
> def : Pat<(f32 (fsqrt (load addr:$src))),<br>
> @@ -3186,49 +3239,11 @@<br>
> (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;<br>
> }<br>
><br>
> -// Square root.<br>
> -defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,<br>
> - SSE_SQRTS>,<br>
> - sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,<br>
> - SSE_SQRTS>;<br>
> -<br>
> -/// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.<br>
> -multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
> - OpndItins itins> {<br>
> - def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),<br>
> - !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),<br>
> - [(set FR32:$dst, (OpNode FR32:$src))]>;<br>
> - // For scalar unary operations, fold a load into the operation<br>
> - // only in OptForSize mode. It eliminates an instruction, but it also<br>
> - // eliminates a whole-register clobber (the load), so it introduces a<br>
> - // partial register update condition.<br>
> - def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),<br>
> - !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),<br>
> - [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,<br>
> - Requires<[UseSSE1, OptForSize]>;<br>
> - let Constraints = "$src1 = $dst" in {<br>
> - def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),<br>
> - (ins VR128:$src1, VR128:$src2),<br>
> - !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),<br>
> - [], itins.rr>;<br>
> - let mayLoad = 1, hasSideEffects = 0 in<br>
> - def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
> - (ins VR128:$src1, ssmem:$src2),<br>
> - !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),<br>
> - [], itins.rm>;<br>
> - }<br>
> -}<br>
> -<br>
> // Reciprocal approximations. Note that these typically require refinement<br>
> // in order to obtain suitable precision.<br>
> -defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>;<br>
> let Predicates = [UseSSE1] in {<br>
> def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),<br>
> (RSQRTSSr_Int VR128:$src, VR128:$src)>;<br>
> -}<br>
> -<br>
> -defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>;<br>
> -let Predicates = [UseSSE1] in {<br>
> def : Pat<(int_x86_sse_rcp_ss VR128:$src),<br>
> (RCPSSr_Int VR128:$src, VR128:$src)>;<br>
> }<br>
><br>
><br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig