Wouldn't it be better to reverse the 'if' condition and reduce the indentation?<br><br><div class="gmail_quote">On Thu, Dec 27, 2012 at 4:47 PM, Nadav Rotem <span dir="ltr"><<a href="mailto:nrotem@apple.com" target="_blank">nrotem@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: nadav<br>
Date: Thu Dec 27 16:47:16 2012<br>
New Revision: 171170<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=171170&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=171170&view=rev</a><br>
Log:<br>
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=171170&r1=171169&r2=171170&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=171170&r1=171169&r2=171170&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 27 16:47:16 2012<br>
@@ -1125,6 +1125,9 @@<br>
setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);<br>
setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);<br>
<br>
+ setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);<br>
+ setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);<br>
+<br>
if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {<br>
setOperationAction(ISD::FMA, MVT::v8f32, Legal);<br>
setOperationAction(ISD::FMA, MVT::v4f64, Legal);<br>
@@ -9539,6 +9542,54 @@<br>
return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));<br>
}<br>
<br>
+SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ EVT VT = Op->getValueType(0);<br>
+ SDValue In = Op->getOperand(0);<br>
+ EVT InVT = In.getValueType();<br>
+ DebugLoc dl = Op->getDebugLoc();<br>
+<br>
+ if ((VT == MVT::v4i64 && InVT == MVT::v4i32) ||<br>
+ (VT == MVT::v8i32 && InVT == MVT::v8i16)) {<br>
+<br>
+ if (Subtarget->hasInt256())<br>
+ return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);<br>
+<br>
+ // Optimize vectors in AVX mode<br>
+ // Sign extend v8i16 to v8i32 and<br>
+ // v4i32 to v4i64<br>
+ //<br>
+ // Divide input vector into two parts<br>
+ // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}<br>
+ // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32<br>
+ // concat the vectors to original VT<br>
+<br>
+ unsigned NumElems = InVT.getVectorNumElements();<br>
+ SDValue Undef = DAG.getUNDEF(InVT);<br>
+<br>
+ SmallVector<int,8> ShufMask1(NumElems, -1);<br>
+ for (unsigned i = 0; i != NumElems/2; ++i)<br>
+ ShufMask1[i] = i;<br>
+<br>
+ SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);<br>
+<br>
+ SmallVector<int,8> ShufMask2(NumElems, -1);<br>
+ for (unsigned i = 0; i != NumElems/2; ++i)<br>
+ ShufMask2[i] = i + NumElems/2;<br>
+<br>
+ SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);<br>
+<br>
+ EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),<br>
+ VT.getVectorNumElements()/2);<br>
+<br>
+ OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);<br>
+ OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);<br>
+<br>
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);<br>
+ }<br>
+ return SDValue();<br>
+}<br>
+<br>
// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or<br>
// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart<br>
// from the AND / OR.<br>
@@ -11809,6 +11860,7 @@<br>
case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);<br>
case ISD::SETCC: return LowerSETCC(Op, DAG);<br>
case ISD::SELECT: return LowerSELECT(Op, DAG);<br>
+ case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);<br>
case ISD::BRCOND: return LowerBRCOND(Op, DAG);<br>
case ISD::JumpTable: return LowerJumpTable(Op, DAG);<br>
case ISD::VASTART: return LowerVASTART(Op, DAG);<br>
@@ -16746,54 +16798,12 @@<br>
return SDValue();<br>
<br>
EVT VT = N->getValueType(0);<br>
- SDValue Op = N->getOperand(0);<br>
- EVT OpVT = Op.getValueType();<br>
- DebugLoc dl = N->getDebugLoc();<br>
-<br>
if (VT.isVector() && VT.getSizeInBits() == 256) {<br>
SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);<br>
if (R.getNode())<br>
return R;<br>
}<br>
<br>
- if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||<br>
- (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {<br>
-<br>
- if (Subtarget->hasInt256())<br>
- return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);<br>
-<br>
- // Optimize vectors in AVX mode<br>
- // Sign extend v8i16 to v8i32 and<br>
- // v4i32 to v4i64<br>
- //<br>
- // Divide input vector into two parts<br>
- // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}<br>
- // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32<br>
- // concat the vectors to original VT<br>
-<br>
- unsigned NumElems = OpVT.getVectorNumElements();<br>
- SDValue Undef = DAG.getUNDEF(OpVT);<br>
-<br>
- SmallVector<int,8> ShufMask1(NumElems, -1);<br>
- for (unsigned i = 0; i != NumElems/2; ++i)<br>
- ShufMask1[i] = i;<br>
-<br>
- SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]);<br>
-<br>
- SmallVector<int,8> ShufMask2(NumElems, -1);<br>
- for (unsigned i = 0; i != NumElems/2; ++i)<br>
- ShufMask2[i] = i + NumElems/2;<br>
-<br>
- SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]);<br>
-<br>
- EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),<br>
- VT.getVectorNumElements()/2);<br>
-<br>
- OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);<br>
- OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);<br>
-<br>
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);<br>
- }<br>
return SDValue();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=171170&r1=171169&r2=171170&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=171170&r1=171169&r2=171170&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Dec 27 16:47:16 2012<br>
@@ -824,6 +824,7 @@<br>
DebugLoc dl, SelectionDAG &DAG) const;<br>
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig