What happened to this section?<br><br>    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },<br>    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },<br>    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },<br>
    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },<br>    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },<br>    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },<br>    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },<br>
    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },<br>    { X86::VHADDPDrr,         X86::VHADDPDrm,          TB_ALIGN_16 },<br>    { X86::VHADDPSrr,         X86::VHADDPSrm,          TB_ALIGN_16 },<br>    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          TB_ALIGN_16 },<br>
    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          TB_ALIGN_16 },<br>    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },<br>    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },<br>    { X86::VMAXPDrr,          X86::VMAXPDrm,           TB_ALIGN_16 },<br>
    { X86::VMAXPDrr_Int,      X86::VMAXPDrm_Int,       TB_ALIGN_16 },<br>    { X86::VMAXPSrr,          X86::VMAXPSrm,           TB_ALIGN_16 },<br>    { X86::VMAXPSrr_Int,      X86::VMAXPSrm_Int,       TB_ALIGN_16 },<br>    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },<br>
    { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },<br>    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },<br>    { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },<br>    { X86::VMINPDrr,          X86::VMINPDrm,           TB_ALIGN_16 },<br>
    { X86::VMINPDrr_Int,      X86::VMINPDrm_Int,       TB_ALIGN_16 },<br>    { X86::VMINPSrr,          X86::VMINPSrm,           TB_ALIGN_16 },<br>    { X86::VMINPSrr_Int,      X86::VMINPSrm_Int,       TB_ALIGN_16 },<br>    { X86::VMINSDrr,          X86::VMINSDrm,           0 },<br>
    { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },<br>    { X86::VMINSSrr,          X86::VMINSSrm,           0 },<br>    { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },<br>    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },<br>
    { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },<br>    { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },<br><br><div class="gmail_quote">On Tue, Dec 25, 2012 at 4:57 PM, Nadav Rotem <span dir="ltr"><<a href="mailto:nrotem@apple.com" target="_blank">nrotem@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Thanks.  We also need to look at the FMA instructions.<br>
<br>
On Dec 25, 2012, at 4:35 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:<br>
<br>
> Author: ctopper<br>
> Date: Tue Dec 25 18:35:47 2012<br>
> New Revision: 171078<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=171078&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=171078&view=rev</a><br>
> Log:<br>
> Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.<br>
><br>
> Modified:<br>
>    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=171078&r1=171077&r2=171078&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=171078&r1=171077&r2=171078&view=diff</a><br>

> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Dec 25 18:35:47 2012<br>
> @@ -852,8 +852,8 @@<br>
>     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },<br>
>     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },<br>
>     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },<br>
> -    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        TB_ALIGN_16 },<br>
> -    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    TB_ALIGN_16 },<br>
> +    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },<br>
> +    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },<br>
>     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },<br>
>     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },<br>
>     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br>
</blockquote></div><br><br clear="all"><br>-- <br>~Craig