<div style="font-family: arial, helvetica, sans-serif; font-size: 10pt"><div dir="ltr">Hey Pawel, please pull this into the release branch. It fixes a release blocker PR filed against one of the RCs.<div><br></div><div style>
(I'm the code owner for SROA fwiw...)</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Sun, Dec 9, 2012 at 4:54 PM, Chandler Carruth <span dir="ltr"><<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: chandlerc<br>
Date: Sun Dec 9 18:54:45 2012<br>
New Revision: 169719<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=169719&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=169719&view=rev</a><br>
Log:<br>
Fix PR14548: SROA was crashing on a mixture of i1 and i8 loads and stores.<br>
<br>
When SROA was evaluating a mixture of i1 and i8 loads and stores, in<br>
just a particular case, it would tickle a latent bug where we compared<br>
bits to bytes rather than bits to bits. As a consequence of the latent<br>
bug, we would allow integers through which were not byte-size multiples,<br>
a situation the later rewriting code was never intended to handle.<br>
<br>
In release builds this could trigger all manner of oddities, but the<br>
reported issue in PR14548 was forming invalid bitcast instructions.<br>
<br>
The only downside of this fix is that it makes it more clear that SROA<br>
in its current form is not capable of handling mixed i1 and i8 loads and<br>
stores. Sometimes with the previous code this would work by luck, but<br>
usually it would crash, so I'm not terribly worried. I'll watch the LNT<br>
numbers just to be sure.<br>
<br>
Modified:<br>
llvm/trunk/lib/Transforms/Scalar/SROA.cpp<br>
llvm/trunk/test/Transforms/SROA/basictest.ll<br>
llvm/trunk/test/Transforms/SROA/big-endian.ll<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/SROA.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SROA.cpp?rev=169719&r1=169718&r2=169719&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SROA.cpp?rev=169719&r1=169718&r2=169719&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/SROA.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/SROA.cpp Sun Dec 9 18:54:45 2012<br>
@@ -2184,7 +2184,7 @@<br>
if (RelBegin == 0 && RelEnd == Size)<br>
WholeAllocaOp = true;<br>
if (IntegerType *ITy = dyn_cast<IntegerType>(LI->getType())) {<br>
- if (ITy->getBitWidth() < TD.getTypeStoreSize(ITy))<br>
+ if (ITy->getBitWidth() < TD.getTypeStoreSizeInBits(ITy))<br>
return false;<br>
continue;<br>
}<br>
@@ -2200,7 +2200,7 @@<br>
if (RelBegin == 0 && RelEnd == Size)<br>
WholeAllocaOp = true;<br>
if (IntegerType *ITy = dyn_cast<IntegerType>(ValueTy)) {<br>
- if (ITy->getBitWidth() < TD.getTypeStoreSize(ITy))<br>
+ if (ITy->getBitWidth() < TD.getTypeStoreSizeInBits(ITy))<br>
return false;<br>
continue;<br>
}<br>
<br>
Modified: llvm/trunk/test/Transforms/SROA/basictest.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SROA/basictest.ll?rev=169719&r1=169718&r2=169719&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SROA/basictest.ll?rev=169719&r1=169718&r2=169719&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/SROA/basictest.ll (original)<br>
+++ llvm/trunk/test/Transforms/SROA/basictest.ll Sun Dec 9 18:54:45 2012<br>
@@ -1147,3 +1147,32 @@<br>
ret void<br>
; CHECK: ret<br>
}<br>
+<br>
+define void @PR14548(i1 %x) {<br>
+; Handle a mixture of i1 and i8 loads and stores to allocas. This particular<br>
+; pattern caused crashes and invalid output in the PR, and its nature will<br>
+; trigger a mixture in several permutations as we resolve each alloca<br>
+; iteratively.<br>
+; Note that we don't do a particularly good *job* of handling these mixtures,<br>
+; but the hope is that this is very rare.<br>
+; CHECK: @PR14548<br>
+<br>
+entry:<br>
+ %a = alloca <{ i1 }>, align 8<br>
+ %b = alloca <{ i1 }>, align 8<br>
+; Nothing of interest is simplified here.<br>
+; CHECK: alloca<br>
+; CHECK: alloca<br>
+<br>
+ %b.i1 = bitcast <{ i1 }>* %b to i1*<br>
+ store i1 %x, i1* %b.i1, align 8<br>
+ %b.i8 = bitcast <{ i1 }>* %b to i8*<br>
+ %foo = load i8* %b.i8, align 1<br>
+<br>
+ %a.i8 = bitcast <{ i1 }>* %a to i8*<br>
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.i8, i8* %b.i8, i32 1, i32 1, i1 false) nounwind<br>
+ %bar = load i8* %a.i8, align 1<br>
+ %a.i1 = getelementptr inbounds <{ i1 }>* %a, i32 0, i32 0<br>
+ %baz = load i1* %a.i1, align 1<br>
+ ret void<br>
+}<br>
<br>
Modified: llvm/trunk/test/Transforms/SROA/big-endian.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SROA/big-endian.ll?rev=169719&r1=169718&r2=169719&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SROA/big-endian.ll?rev=169719&r1=169718&r2=169719&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/SROA/big-endian.ll (original)<br>
+++ llvm/trunk/test/Transforms/SROA/big-endian.ll Sun Dec 9 18:54:45 2012<br>
@@ -82,14 +82,9 @@<br>
<br>
%a0i16ptr = bitcast i8* %a0ptr to i16*<br>
store i16 1, i16* %a0i16ptr<br>
-; CHECK: %[[mask0:.*]] = and i16 1, -16<br>
-<br>
- %a1i4ptr = bitcast i8* %a1ptr to i4*<br>
- store i4 1, i4* %a1i4ptr<br>
-; CHECK-NEXT: %[[insert0:.*]] = or i16 %[[mask0]], 1<br>
<br>
store i8 1, i8* %a2ptr<br>
-; CHECK-NEXT: %[[mask1:.*]] = and i40 undef, 4294967295<br>
+; CHECK: %[[mask1:.*]] = and i40 undef, 4294967295<br>
; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], 4294967296<br>
<br>
%a3i24ptr = bitcast i8* %a3ptr to i24*<br>
@@ -110,7 +105,7 @@<br>
%ai = load i56* %aiptr<br>
%ret = zext i56 %ai to i64<br>
ret i64 %ret<br>
-; CHECK-NEXT: %[[ext4:.*]] = zext i16 %[[insert0]] to i56<br>
+; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56<br>
; CHECK-NEXT: %[[shift4:.*]] = shl i56 %[[ext4]], 40<br>
; CHECK-NEXT: %[[mask4:.*]] = and i56 %[[insert3]], 1099511627775<br>
; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[shift4]]<br>
<br>
<br>
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</blockquote></div><br></div></div>