<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi Pawel,<div><br></div><div>Would you merge this bugfix to the release branch, please?<br><div><br></div><div>I am the code owner.</div><div><br></div><div>Thanks,</div><div>/jakob</div><div><br><div>Begin forwarded message:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px;"><span style="font-family:'Helvetica'; font-size:medium; color:rgba(0, 0, 0, 1.0);"><b>From: </b></span><span style="font-family:'Helvetica'; font-size:medium;">Jakob Stoklund Olesen <<a href="mailto:stoklund@2pi.dk">stoklund@2pi.dk</a>><br></span></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px;"><span style="font-family:'Helvetica'; font-size:medium; color:rgba(0, 0, 0, 1.0);"><b>Subject: </b></span><span style="font-family:'Helvetica'; font-size:medium;"><b>[llvm-commits] [llvm] r168837 - in /llvm/trunk: lib/CodeGen/RegisterCoalescer.cpp test/CodeGen/ARM/coalesce-subregs.ll</b><br></span></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px;"><span style="font-family:'Helvetica'; font-size:medium; color:rgba(0, 0, 0, 1.0);"><b>Date: </b></span><span style="font-family:'Helvetica'; font-size:medium;">November 28, 2012 4:26:12 PM PST<br></span></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px;"><span style="font-family:'Helvetica'; font-size:medium; color:rgba(0, 0, 0, 1.0);"><b>To: </b></span><span style="font-family:'Helvetica'; font-size:medium;"><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></span></div><br><div>Author: stoklund<br>Date: Wed Nov 28 18:26:11 2012<br>New Revision: 168837<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=168837&view=rev">http://llvm.org/viewvc/llvm-project?rev=168837&view=rev</a><br>Log:<br>Avoid rewriting instructions twice.<br><br>This could cause miscompilations in targets where sub-register<br>composition is not always idempotent (ARM).<br><br><<a href="rdar://problem/12758887">rdar://problem/12758887</a>><br><br>Modified:<br> llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp<br> llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll<br><br>Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=168837&r1=168836&r2=168837&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=168837&r1=168836&r2=168837&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Nov 28 18:26:11 2012<br>@@ -887,8 +887,17 @@<br> // Update LiveDebugVariables.<br> LDV->renameRegister(SrcReg, DstReg, SubIdx);<br><br>+ SmallPtrSet<MachineInstr*, 8> Visited;<br> for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);<br> MachineInstr *UseMI = I.skipInstruction();) {<br>+ // Each instruction can only be rewritten once because sub-register<br>+ // composition is not always idempotent. When SrcReg != DstReg, rewriting<br>+ // the UseMI operands removes them from the SrcReg use-def chain, but when<br>+ // SrcReg is DstReg we could encounter UseMI twice if it has multiple<br>+ // operands mentioning the virtual register.<br>+ if (SrcReg == DstReg && !Visited.insert(UseMI))<br>+ continue;<br>+<br> SmallVector<unsigned,8> Ops;<br> bool Reads, Writes;<br> tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);<br><br>Modified: llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll?rev=168837&r1=168836&r2=168837&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll?rev=168837&r1=168836&r2=168837&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll Wed Nov 28 18:26:11 2012<br>@@ -317,3 +317,44 @@<br> store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128<br> ret void<br> }<br>+<br>+; <<a href="rdar://problem/12758887">rdar://problem/12758887</a>><br>+; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than<br>+; once under rare circumstances. When widening a register from QPR to DTriple<br>+; with the original virtual register in dsub_1_dsub_2, the double rewrite would<br>+; produce an invalid sub-register.<br>+;<br>+; This is because dsub_1_dsub_2 is not an idempotent sub-register index.<br>+; It will translate %vr:dsub_0 -> %vr:dsub_1.<br>+define hidden fastcc void @radar12758887() nounwind optsize ssp {<br>+entry:<br>+ br i1 undef, label %for.body, label %for.end70<br>+<br>+for.body: ; preds = %for.end, %entry<br>+ br i1 undef, label %for.body29, label %for.end<br>+<br>+for.body29: ; preds = %for.body29, %for.body<br>+ %0 = load <2 x double>* null, align 1<br>+ %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer<br>+ %mul41 = fmul <2 x double> undef, %splat40<br>+ %add42 = fadd <2 x double> undef, %mul41<br>+ %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1><br>+ %mul45 = fmul <2 x double> undef, %splat44<br>+ %add46 = fadd <2 x double> undef, %mul45<br>+ br i1 undef, label %for.end, label %for.body29<br>+<br>+for.end: ; preds = %for.body29, %for.body<br>+ %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]<br>+ %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]<br>+ %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0><br>+ %add58 = fadd <2 x double> undef, %1<br>+ %mul61 = fmul <2 x double> %add58, undef<br>+ %add63 = fadd <2 x double> undef, %mul61<br>+ %add64 = fadd <2 x double> undef, %add63<br>+ %add67 = fadd <2 x double> undef, %add64<br>+ store <2 x double> %add67, <2 x double>* undef, align 1<br>+ br i1 undef, label %for.end70, label %for.body<br>+<br>+for.end70: ; preds = %for.end, %entry<br>+ ret void<br>+}<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>