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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks!<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Committed revision 168207.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jim Grosbach [mailto:grosbach@apple.com] <br><b>Sent:</b> Friday, November 16, 2012 10:32 AM<br><b>To:</b> weimingz@codeaurora.org<br><b>Cc:</b> 'Jakob Stoklund Olesen'; llvm-commits@cs.uiuc.edu; zinob@codeaurora.org<br><b>Subject:</b> Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Looks good to me. Please commit.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>-Jim<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Nov 16, 2012, at 10:03 AM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Jim,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I addressed the stylistic issues.</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I plan to fix some existing naming issues (at least for PairSRegs, PairDRegs, PairQRegs) as a follow up patch.</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Weiming</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><o:p></o:p></p></div></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><div><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span class=apple-converted-space><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> </span></span><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>Jim Grosbach [mailto:grosbach@<a href="http://apple.com"><span style='color:purple'>apple.com</span></a>]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Thursday, November 15, 2012 1:22 PM<br><b>To:</b><span class=apple-converted-space> </span><a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a><br><b>Cc:</b><span class=apple-converted-space> </span>'Jakob Stoklund Olesen';<span class=apple-converted-space> </span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:purple'>llvm-commits@cs.uiuc.edu</span></a>;<span class=apple-converted-space> </span><a href="mailto:zinob@codeaurora.org"><span style='color:purple'>zinob@codeaurora.org</span></a><br><b>Subject:</b><span class=apple-converted-space> </span>Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM</span><o:p></o:p></p></div></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><p class=MsoNormal>Hi Weiming,<o:p></o:p></p></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>A few stylistic notes are the only cleanups I'd like to see. The core code is looking great. <o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><p class=MsoNormal>Jakob, do you have any additional changes you would like to see?<o:p></o:p></p></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>-Jim<o:p></o:p></p></div><div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>+/// PairRRegs - Form a GPRPair pseudo register from a pair of G registers.<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+///<o:p></o:p></p></div></div></blockquote></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>The DOxygen style preferences have changed a bit recently. Have a look at <a href="http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments"><span style='color:purple'>http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments</span></a> for the gory details.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>+SDNode *ARMDAGToDAGISel::PairGRegs(EVT VT, SDValue V0, SDValue V1) {<o:p></o:p></p></div></blockquote></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>This function name could be clearer and should adhere to the coding syle guidelines (start w/ a verb, camel-case w/ the first letter being lower case). Something like createGPRPairNode(), perhaps.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>+ DebugLoc dl = V0.getNode()->getDebugLoc();<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ SDValue RegClass =<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+}<o:p></o:p></p></div></div></blockquote></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>--- a/lib/Target/ARM/ARMISelLowering.cpp<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+++ b/lib/Target/ARM/ARMISelLowering.cpp<o:p></o:p></p></div></div><div><div><p class=MsoNormal>@@ -5771,12 +5771,16 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,<o:p></o:p></p></div></div><div><div><p class=MsoNormal> // for ldrexd must be different.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> BB = loopMBB;<o:p></o:p></p></div></div><div><div><p class=MsoNormal> // Load<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ unsigned gpair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ unsigned gpair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+<o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Variables should start with upper case. Perhaps RegPair0 and RegPair? Yes, some of the surrounding code sets a bad example about this. :( Fixing some of that as a separate follow-up patch would be very welcome (though in no way required for this patch to go in).<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>+<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+ unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);<o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Ditto. Perhaps UndefPair?<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>-Jim<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><div><p class=MsoNormal>On Nov 2, 2012, at 10:08 AM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a>> wrote:<o:p></o:p></p></div></div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><div><p class=MsoNormal>Hi Jim,<br><br>Thanks for your review and suggestion.<br>RegisterOperand does make the code cleaner. I also add more explanations on<br>Disassembler and AsmParser.<br><br>Please help to review.<br><br>Thanks,<br>Weiming<br><br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by<br>The Linux Foundation<br><br><br>-----Original Message-----<br>From: Jim Grosbach [mailto:grosbach@<a href="http://apple.com"><span style='color:purple'>apple.com</span></a>]<span class=apple-converted-space> </span><br>Sent: Thursday, November 01, 2012 5:16 PM<br>To:<span class=apple-converted-space> </span><a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a><br>Cc: 'Jakob Stoklund Olesen';<span class=apple-converted-space> </span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:purple'>llvm-commits@cs.uiuc.edu</span></a>;<span class=apple-converted-space> </span><a href="mailto:zinob@codeaurora.org"><span style='color:purple'>zinob@codeaurora.org</span></a><br>Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm<br>with 64-bit data on ARM<br><br>Hi Weiming,<br><br>You may want to consider a RegisterOperand here, which allows a custom print<br>method on a register class. You can just use the RegisterOperand wherever<br>you'd normally use a RegisterClass in the (ins) and (outs) lists. For<br>example, def GPRPairOp : RegisterOperand<GPRPair, "printGPRPair">;<br><br>Then the printOperand() method doesn't need to perform the special "is this<br>a gprpair?" check for every register operand, which is a speed improvement<br>on the common path. There's a dedicated print method that's only used for<br>these operands.<br><br>The asm parser bit seems ok. It's a pretty ugly hack, but that's somewhat<br>necessary at this stage, as the parsers don't have any way to express these<br>kinds of constraints, so we have to do it manually in C++ code. Please add a<br>FIXME there with a very descriptive comment about why this is necessary.<br><br>-Jim<br><br>On Nov 1, 2012, at 3:35 PM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a>> wrote:<br><br><br><br><o:p></o:p></p></div><div><p class=MsoNormal>Hi Jakob & Jim,<br><br>I updated the instruction def of ldrexd/strexd to let them use GPRPair<span class=apple-converted-space> </span><br>Reg class.<br>I also fixed ldrexd/strexd intrinsics and atomic_64 lowering accordingly.<br>Disassembler and AsmParser are adjusted to fit the new instruction def.<br>The original test case "atomic-64bit.ll" is updated, so it's not<span class=apple-converted-space> </span><br>checking hardcoded R0,R1 or R2,R3<br><br>It passes the "make check", especially atomic-64bit.ll, ldstrexd,ll,<span class=apple-converted-space> </span><br>MC/ARM/basic-asm-instrucions.s, MC/ARM/diagnstics.s and<span class=apple-converted-space> </span><br>MC/Disassembler/ARM/ basic-arm-instructions.txt<br><br>Please help to review it.<br><br>Thanks,<br>Weiming<br><br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,<span class=apple-converted-space> </span><br>hosted by The Linux Foundation<br><br><br>-----Original Message-----<br>From: Jim Grosbach [mailto:grosbach@<a href="http://apple.com"><span style='color:purple'>apple.com</span></a>]<br>Sent: Wednesday, October 31, 2012 3:24 PM<br>To: Jakob Stoklund Olesen<br>Cc:<span class=apple-converted-space> </span><a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a>;<span class=apple-converted-space> </span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:purple'>llvm-commits@cs.uiuc.edu</span></a>;<span class=apple-converted-space> </span><br><a href="mailto:zinob@codeaurora.org"><span style='color:purple'>zinob@codeaurora.org</span></a><br>Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for<span class=apple-converted-space> </span><br>inline asm with 64-bit data on ARM<br><br><br>On Oct 31, 2012, at 3:17 PM, Jakob Stoklund Olesen <<a href="mailto:stoklund@2pi.dk"><span style='color:purple'>stoklund@2pi.dk</span></a>><o:p></o:p></p></div><div><p class=MsoNormal>wrote:<br><br><br><o:p></o:p></p></div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><div><p class=MsoNormal><br>On Oct 31, 2012, at 3:15 PM, "Weiming Zhao" <<a href="mailto:weimingz@codeaurora.org"><span style='color:purple'>weimingz@codeaurora.org</span></a>><o:p></o:p></p></div><div><p class=MsoNormal>wrote:<br><br><br><o:p></o:p></p></div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><div><p class=MsoNormal>Hi Jakob,<br><br>I'm changing the ldrexd/strexd of ARMInstrInfo.td to def LDREXD:<span class=apple-converted-space> </span><br>AIldrex<0b01, (outs GPRPair:$Rt),(ins addr_offset_none:$addr),<br> NoItinerary, "ldrexd", "\t$Rt, $addr", []> { let<span class=apple-converted-space> </span><br>DecoderMethod = "DecodeDoubleRegLoad"; }<br><br>def STREXD : AIstrex<0b01, (outs GPR:$Rd),<br> (ins GPRPair:$Rt, addr_offset_none:$addr),<br> NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {<span class=apple-converted-space> </span><br>let DecoderMethod = "DecodeDoubleRegStore"; }<br><br>Is this the way you're referring to?<o:p></o:p></p></div><div><p class=MsoNormal><br>Exactly.<br><br><br><br><o:p></o:p></p></div><div><p class=MsoNormal>So far, it almost works but I need to deal with printing "R0_R1" for<span class=apple-converted-space> </span><br>the GPRPair reg name. I'm planning to do it in<span class=apple-converted-space> </span><br>InstPrinter/ARMInstPrinter.cpp::printOperand().<o:p></o:p></p></div><div><p class=MsoNormal><br>I think that's right. Jim?<o:p></o:p></p></div><div><p class=MsoNormal><br>Sure, that'll work. Changing the instruction definitions like this<span class=apple-converted-space> </span><br>will require some work in the AsmParser, too, though. I'm surprised<span class=apple-converted-space> </span><br>you're not seeing a "make check" failure on basic-arm-instructions.s<span class=apple-converted-space> </span><br>with these changes.<br><br>-Jim<br><0002-Remove-hard-coded-registers-in-ARM-ldrexd-and-strexd.patch><o:p></o:p></p></div><div><p class=MsoNormal><br><0003-Remove-hard-coded-registers-in-ARM-ldrexd-and-strexd.patch><o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div></div><p class=MsoNormal><span style='font-size:13.5pt;font-family:"Helvetica","sans-serif"'><0004-Remove-hard-coded-registers-in-ARM-ldrexd-and-strexd.patch><o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>