Pawel,<div><br></div><div>Can you merge this into the 3.2 branch? It's a bug fix.</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Nov 14, 2012 at 2:46 PM, Justin Holewinski <span dir="ltr"><<a href="mailto:justin.holewinski@gmail.com" target="_blank">justin.holewinski@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">As this is a bug fix, can we get this merged into the 3.2 branch?<div class="gmail_extra"><div><div class="h5"><br><br>
<div class="gmail_quote">On Wed, Nov 14, 2012 at 2:19 PM, Justin Holewinski <span dir="ltr"><<a href="mailto:jholewinski@nvidia.com" target="_blank">jholewinski@nvidia.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jholewinski<br>
Date: Wed Nov 14 13:19:16 2012<br>
New Revision: 167948<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=167948&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=167948&view=rev</a><br>
Log:<br>
[NVPTX] Implement custom lowering of loads/stores for i1<br>
<br>
Loads from i1 become loads from i8 followed by trunc<br>
Stores to i1 become zext to i8 followed by store to i8<br>
<br>
Fixes PR13291<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll<br>
Modified:<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=167948&r1=167947&r2=167948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=167948&r1=167947&r2=167948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Wed Nov 14 13:19:16 2012<br>
@@ -174,10 +174,11 @@<br>
setTruncStoreAction(MVT::f64, MVT::f32, Expand);<br>
<br>
// PTX does not support load / store predicate registers<br>
- setOperationAction(ISD::LOAD, MVT::i1, Expand);<br>
+ setOperationAction(ISD::LOAD, MVT::i1, Custom);<br>
+ setOperationAction(ISD::STORE, MVT::i1, Custom);<br>
+<br>
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);<br>
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);<br>
- setOperationAction(ISD::STORE, MVT::i1, Expand);<br>
setTruncStoreAction(MVT::i64, MVT::i1, Expand);<br>
setTruncStoreAction(MVT::i32, MVT::i1, Expand);<br>
setTruncStoreAction(MVT::i16, MVT::i1, Expand);<br>
@@ -856,11 +857,66 @@<br>
case ISD::EXTRACT_SUBVECTOR:<br>
return Op;<br>
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);<br>
+ case ISD::STORE: return LowerSTORE(Op, DAG);<br>
+ case ISD::LOAD: return LowerLOAD(Op, DAG);<br>
default:<br>
llvm_unreachable("Custom lowering not defined for operation");<br>
}<br>
}<br>
<br>
+<br>
+// v = ld i1* addr<br>
+// =><br>
+// v1 = ld i8* addr<br>
+// v = trunc v1 to i1<br>
+SDValue NVPTXTargetLowering::<br>
+LowerLOAD(SDValue Op, SelectionDAG &DAG) const {<br>
+ SDNode *Node = Op.getNode();<br>
+ LoadSDNode *LD = cast<LoadSDNode>(Node);<br>
+ DebugLoc dl = Node->getDebugLoc();<br>
+ ISD::LoadExtType ExtType = LD->getExtensionType();<br>
+ assert(ExtType == ISD::NON_EXTLOAD) ;<br>
+ EVT VT = Node->getValueType(0);<br>
+ assert(VT == MVT::i1 && "Custom lowering for i1 load only");<br>
+ SDValue newLD = DAG.getLoad(MVT::i8, dl, LD->getChain(), LD->getBasePtr(),<br>
+ LD->getPointerInfo(),<br>
+ LD->isVolatile(), LD->isNonTemporal(),<br>
+ LD->isInvariant(),<br>
+ LD->getAlignment());<br>
+ SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);<br>
+ // The legalizer (the caller) is expecting two values from the legalized<br>
+ // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()<br>
+ // in LegalizeDAG.cpp which also uses MergeValues.<br>
+ SDValue Ops[] = {result, LD->getChain()};<br>
+ return DAG.getMergeValues(Ops, 2, dl);<br>
+}<br>
+<br>
+// st i1 v, addr<br>
+// =><br>
+// v1 = zxt v to i8<br>
+// st i8, addr<br>
+SDValue NVPTXTargetLowering::<br>
+LowerSTORE(SDValue Op, SelectionDAG &DAG) const {<br>
+ SDNode *Node = Op.getNode();<br>
+ DebugLoc dl = Node->getDebugLoc();<br>
+ StoreSDNode *ST = cast<StoreSDNode>(Node);<br>
+ SDValue Tmp1 = ST->getChain();<br>
+ SDValue Tmp2 = ST->getBasePtr();<br>
+ SDValue Tmp3 = ST->getValue();<br>
+ EVT VT = Tmp3.getValueType();<br>
+ assert(VT == MVT::i1 && "Custom lowering for i1 store only");<br>
+ unsigned Alignment = ST->getAlignment();<br>
+ bool isVolatile = ST->isVolatile();<br>
+ bool isNonTemporal = ST->isNonTemporal();<br>
+ Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl,<br>
+ MVT::i8, Tmp3);<br>
+ SDValue Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,<br>
+ ST->getPointerInfo(), isVolatile,<br>
+ isNonTemporal, Alignment);<br>
+ return Result;<br>
+}<br>
+<br>
+<br>
SDValue<br>
NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname, int idx,<br>
EVT v) const {<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h?rev=167948&r1=167947&r2=167948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h?rev=167948&r1=167947&r2=167948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h Wed Nov 14 13:19:16 2012<br>
@@ -138,6 +138,9 @@<br>
SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);<br>
<br>
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;<br>
+<br>
+ SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;<br>
};<br>
} // namespace llvm<br>
<br>
<br>
Added: llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll?rev=167948&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll?rev=167948&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll (added)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/pr13291-i1-store.ll Wed Nov 14 13:19:16 2012<br>
@@ -0,0 +1,26 @@<br>
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32<br>
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64<br>
+<br>
+define ptx_kernel void @t1(i1* %a) {<br>
+; PTX32: mov.u16 %rc{{[0-9]+}}, 0;<br>
+; PTX32-NEXT: st.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}};<br>
+; PTX64: mov.u16 %rc{{[0-9]+}}, 0;<br>
+; PTX64-NEXT: st.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}};<br>
+ store i1 false, i1* %a<br>
+ ret void<br>
+}<br>
+<br>
+<br>
+define ptx_kernel void @t2(i1* %a, i8* %b) {<br>
+; PTX32: ld.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]<br>
+; PTX32: and.b16 temp, %rc{{[0-9]+}}, 1;<br>
+; PTX32: setp.b16.eq %p{{[0-9]+}}, temp, 1;<br>
+; PTX64: ld.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]<br>
+; PTX64: and.b16 temp, %rc{{[0-9]+}}, 1;<br>
+; PTX64: setp.b16.eq %p{{[0-9]+}}, temp, 1;<br>
+<br>
+ %t1 = load i1* %a<br>
+ %t2 = select i1 %t1, i8 1, i8 2<br>
+ store i8 %t2, i8* %b<br>
+ ret void<br>
+}<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div></div></div><span class="HOEnZb"><font color="#888888">-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div><br>
</font></span></div>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div><br>
</div>