<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi Weiming,<div><br></div><div>A few stylistic notes are the only cleanups I'd like to see. The core code is looking great. </div><div><br></div>Jakob, do you have any additional changes you would like to see?<div><br></div><div>-Jim<br><div><br><div><div><blockquote type="cite"><div>+/// PairRRegs - Form a GPRPair pseudo register from a pair of G registers.</div><div>+///</div></blockquote></div><div><br></div><div>The DOxygen style preferences have changed a bit recently. Have a look at <a href="http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments">http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments</a> for the gory details.</div><div><br></div><div><blockquote type="cite">+SDNode *ARMDAGToDAGISel::PairGRegs(EVT VT, SDValue V0, SDValue V1) {</blockquote></div><div><br></div><div>This function name could be clearer and should adhere to the coding syle guidelines (start w/ a verb, camel-case w/ the first letter being lower case). Something like createGPRPairNode(), perhaps.</div><div><br></div><div><blockquote type="cite"><div>+ DebugLoc dl = V0.getNode()->getDebugLoc();</div><div>+ SDValue RegClass =</div><div>+ CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);</div><div>+ SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);</div><div>+ SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);</div><div>+ const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };</div><div>+ return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);</div><div>+}</div></blockquote></div></div><div><br></div><div><blockquote type="cite"><div>--- a/lib/Target/ARM/ARMISelLowering.cpp</div><div>+++ b/lib/Target/ARM/ARMISelLowering.cpp</div><div>@@ -5771,12 +5771,16 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,</div><div> // for ldrexd must be different.</div><div> BB = loopMBB;</div><div> // Load</div><div>+ unsigned gpair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);</div><div>+ unsigned gpair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);</div><div>+</div></blockquote><br></div><div>Variables should start with upper case. Perhaps RegPair0 and RegPair? Yes, some of the surrounding code sets a bad example about this. :( Fixing some of that as a separate follow-up patch would be very welcome (though in no way required for this patch to go in).</div><div><br></div><div><blockquote type="cite"><div>+</div><div>+ unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);</div></blockquote><br></div><div>Ditto. Perhaps UndefPair?</div><div><br></div><div>-Jim</div><div><br></div><div><br><div><div>On Nov 2, 2012, at 10:08 AM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Hi Jim,<br><br>Thanks for your review and suggestion.<br>RegisterOperand does make the code cleaner. I also add more explanations on<br>Disassembler and AsmParser.<br><br>Please help to review.<br><br>Thanks,<br>Weiming<br><br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by<br>The Linux Foundation<br><br><br>-----Original Message-----<br>From: Jim Grosbach [mailto:grosbach@<a href="http://apple.com">apple.com</a>] <br>Sent: Thursday, November 01, 2012 5:16 PM<br>To: <a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a><br>Cc: 'Jakob Stoklund Olesen'; <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a>; <a href="mailto:zinob@codeaurora.org">zinob@codeaurora.org</a><br>Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm<br>with 64-bit data on ARM<br><br>Hi Weiming,<br><br>You may want to consider a RegisterOperand here, which allows a custom print<br>method on a register class. You can just use the RegisterOperand wherever<br>you'd normally use a RegisterClass in the (ins) and (outs) lists. For<br>example, def GPRPairOp : RegisterOperand<GPRPair, "printGPRPair">;<br><br>Then the printOperand() method doesn't need to perform the special "is this<br>a gprpair?" check for every register operand, which is a speed improvement<br>on the common path. There's a dedicated print method that's only used for<br>these operands.<br><br>The asm parser bit seems ok. It's a pretty ugly hack, but that's somewhat<br>necessary at this stage, as the parsers don't have any way to express these<br>kinds of constraints, so we have to do it manually in C++ code. Please add a<br>FIXME there with a very descriptive comment about why this is necessary.<br><br>-Jim<br><br>On Nov 1, 2012, at 3:35 PM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> wrote:<br><br><blockquote type="cite">Hi Jakob & Jim,<br><br>I updated the instruction def of ldrexd/strexd to let them use GPRPair <br>Reg class.<br>I also fixed ldrexd/strexd intrinsics and atomic_64 lowering accordingly.<br>Disassembler and AsmParser are adjusted to fit the new instruction def.<br>The original test case "atomic-64bit.ll" is updated, so it's not <br>checking hardcoded R0,R1 or R2,R3<br><br>It passes the "make check", especially atomic-64bit.ll, ldstrexd,ll, <br>MC/ARM/basic-asm-instrucions.s, MC/ARM/diagnstics.s and <br>MC/Disassembler/ARM/ basic-arm-instructions.txt<br><br>Please help to review it.<br><br>Thanks,<br>Weiming<br><br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, <br>hosted by The Linux Foundation<br><br><br>-----Original Message-----<br>From: Jim Grosbach [mailto:grosbach@<a href="http://apple.com">apple.com</a>]<br>Sent: Wednesday, October 31, 2012 3:24 PM<br>To: Jakob Stoklund Olesen<br>Cc: <a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>; <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a>; <br><a href="mailto:zinob@codeaurora.org">zinob@codeaurora.org</a><br>Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for <br>inline asm with 64-bit data on ARM<br><br><br>On Oct 31, 2012, at 3:17 PM, Jakob Stoklund Olesen <stoklund@2pi.dk><br></blockquote>wrote:<br><blockquote type="cite"><br><blockquote type="cite"><br>On Oct 31, 2012, at 3:15 PM, "Weiming Zhao" <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>><br></blockquote>wrote:<br><blockquote type="cite"><br><blockquote type="cite">Hi Jakob,<br><br>I'm changing the ldrexd/strexd of ARMInstrInfo.td to def LDREXD: <br>AIldrex<0b01, (outs GPRPair:$Rt),(ins addr_offset_none:$addr),<br> NoItinerary, "ldrexd", "\t$Rt, $addr", []> { let <br>DecoderMethod = "DecodeDoubleRegLoad"; }<br><br>def STREXD : AIstrex<0b01, (outs GPR:$Rd),<br> (ins GPRPair:$Rt, addr_offset_none:$addr),<br> NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { <br>let DecoderMethod = "DecodeDoubleRegStore"; }<br><br>Is this the way you're referring to?<br></blockquote><br>Exactly.<br><br><blockquote type="cite">So far, it almost works but I need to deal with printing "R0_R1" for <br>the GPRPair reg name. I'm planning to do it in <br>InstPrinter/ARMInstPrinter.cpp::printOperand().<br></blockquote><br>I think that's right. Jim?<br></blockquote><br>Sure, that'll work. Changing the instruction definitions like this <br>will require some work in the AsmParser, too, though. I'm surprised <br>you're not seeing a "make check" failure on basic-arm-instructions.s <br>with these changes.<br><br>-Jim<br><0002-Remove-hard-coded-registers-in-ARM-ldrexd-and-strexd.patch><br></blockquote><br><span><0003-Remove-hard-coded-registers-in-ARM-ldrexd-and-strexd.patch></span></blockquote></div><br></div></div></div></body></html>