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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Was there a bug filed for the original failure?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I don’t think it is a good idea to quietly silence failures like these by inserting a work around. A failure in instruction selection is an important signal that we are potentially missing a pattern. We should address the root cause by adding a pattern to select the correct instruction rather than just inserting a work around. I expect we will see more failures like this as the vectorizer stresses the back ends and we need to stay on top of them so that we generate good quality code.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Do you perhaps have a small test case we can use to file a bug as a reminder to investigate this issue?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-- </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Craig Topper [mailto:craig.topper@gmail.com] <br><b>Sent:</b> Thursday, November 15, 2012 11:35 AM<br><b>To:</b> David Peixotto<br><b>Cc:</b> llvm-commits@cs.uiuc.edu<br><b>Subject:</b> Re: [llvm-commits] [llvm] r168029 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>My primary goal was to keep instruction selection from failing. Without the change I made, FABS of v4f32 just didn't match anything and failed. Someone familiar with ARM could maybe do something better.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Thu, Nov 15, 2012 at 9:52 AM, David Peixotto <<a href="mailto:dpeixott@codeaurora.org" target="_blank">dpeixott@codeaurora.org</a>> wrote:<o:p></o:p></p><p class=MsoNormal style='margin-bottom:12.0pt'>Hi Craig,<br><br>I see the change was reverted for FNEG, but what about FABS? Why does FABS<br>need to be marked as expand here? There is a VABS.f32 instruction that<br>operates on Q registers that should work for a v4f32 type. Will that<br>instruction be generated when it is marked expand?<br><br>Thanks,<br>David<br><br>-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted<br>by The Linux Foundation<br><br><br>> -----Original Message-----<br>> From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-">llvm-commits-</a><br>> <a href="mailto:bounces@cs.uiuc.edu">bounces@cs.uiuc.edu</a>] On Behalf Of Craig Topper<br>> Sent: Thursday, November 15, 2012 12:06 AM<br>> To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>> Subject: [llvm-commits] [llvm] r168029 -<br>> /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>><br>> Author: ctopper<br>> Date: Thu Nov 15 02:06:12 2012<br>> New Revision: 168029<br>><br>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=168029&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=168029&view=rev</a><br>> Log:<br>> Make FNEG and FABS of v4f32 Expand.<br>><br>> Modified:<br>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>><br>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-" target="_blank">http://llvm.org/viewvc/llvm-</a><br>> project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=168029&r1=1<br>> 68028&r2=168029&view=diff<br>> ==========================================================<br>> ====================<br>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Nov 15 02:06:12<br>> 2012<br>> @@ -505,6 +505,8 @@<br>> setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);<br>> setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);<br>><br>> + setOperationAction(ISD::FNEG, MVT::v4f32, Expand);<br>> + setOperationAction(ISD::FABS, MVT::v4f32, Expand);<br>> setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);<br>> setOperationAction(ISD::FSIN, MVT::v4f32, Expand);<br>> setOperationAction(ISD::FCOS, MVT::v4f32, Expand);<br>><br>><br>> _______________________________________________<br>> llvm-commits mailing list<br>> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- <br>~Craig<o:p></o:p></p></div></div></div></body></html>