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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>What does this error mean? This is a new .ll test and it worked for me in my local ‘make check-all’. Do you think I should to revert the patch?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Jyotsna<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>--<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> NAKAMURA Takumi [mailto:geek4civic@gmail.com] <br><b>Sent:</b> Wednesday, November 14, 2012 4:11 PM<br><b>To:</b> Jyotsna Verma<br><b>Cc:</b> llvm-commits<br><b>Subject:</b> Re: [llvm-commits] [llvm] r167974 - in /llvm/trunk: lib/Target/Hexagon/HexagonInstrFormats.td lib/Target/Hexagon/HexagonInstrInfo.td lib/Target/Hexagon/HexagonInstrInfoV4.td lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h test/CodeGen/Hexagon/postinc-lo<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Jyotsna, I tried to bisecting, but I didn't find any other trigger.<o:p></o:p></p><div><p class=MsoNormal>I guess something would be wrong in hexagon.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>FYI, also i386-freebsd blames.<o:p></o:p></p></div><div><p class=MsoNormal><a href="http://llvm-amd64.freebsd.your.org:8010/builders/clang-i386-freebsd/builds/7744">http://llvm-amd64.freebsd.your.org:8010/builders/clang-i386-freebsd/builds/7744</a><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>...Takumi<o:p></o:p></p></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2012/11/15 NAKAMURA Takumi <<a href="mailto:geek4civic@gmail.com" target="_blank">geek4civic@gmail.com</a>><o:p></o:p></p><p class=MsoNormal>Jyotsna, it seems it crashes on i686 hosts.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>On i686-mingw32,<o:p></o:p></p></div><div><p class=MsoNormal><a href="http://bb.pgr.jp/builders/cmake-clang-i686-mingw32/builds/2906" target="_blank">http://bb.pgr.jp/builders/cmake-clang-i686-mingw32/builds/2906</a><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>On i686-linux,<o:p></o:p></p></div><div><div><p class=MsoNormal>--<o:p></o:p></p></div><div><p class=MsoNormal>Exit Code: 1<o:p></o:p></p></div><div><p class=MsoNormal>Command Output (stderr):<o:p></o:p></p></div><div><p class=MsoNormal>--<o:p></o:p></p></div><div><p class=MsoNormal>llc: /home/chapuni/llvm-project/llvm/lib/VMCore/DebugLoc.cpp:60: void llvm::DebugLoc::getScopeAndInlinedAt(llvm::MDNode*&, llvm::MDNode*&, const llvm::LLVMContext&) const: Assertion `unsigned(ScopeIdx) <= Ctx.pImpl->ScopeRecords.size() && "Invalid ScopeIdx!"' failed.<o:p></o:p></p></div><div><p class=MsoNormal>0 llc 0x08d3fec8<o:p></o:p></p></div><div><p class=MsoNormal>Stack dump:<o:p></o:p></p></div><div><p class=MsoNormal>0. Program arguments: /home/chapuni/BUILD/i686-autoconf/Release+Asserts/bin/llc -march=hexagon -mcpu=hexagonv4<o:p></o:p></p></div><div><p class=MsoNormal>1. Running pass 'Function Pass Manager' on module '<stdin>'.<o:p></o:p></p></div><div><p class=MsoNormal>2. Running pass 'Debug Variable Analysis' on function '@sum'<o:p></o:p></p></div></div><div><div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2012/11/15 Jyotsna Verma <<a href="mailto:jverma@codeaurora.org" target="_blank">jverma@codeaurora.org</a>><o:p></o:p></p><p class=MsoNormal>Author: jverma<br>Date: Wed Nov 14 14:38:48 2012<br>New Revision: 167974<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=167974&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=167974&view=rev</a><br>Log:<br>Added multiclass for post-increment load instructions.<br><br>Added:<br> llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll<br>Modified:<br> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=167974&r1=167973&r2=167974&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=167974&r1=167973&r2=167974&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Wed Nov 14 14:38:48 2012<br>@@ -27,6 +27,34 @@<br> def TypeXTYPE : Type<8>;<br> def TypeMARKER : Type<31>;<br><br>+// Maintain list of valid subtargets for each instruction.<br>+class SubTarget<bits<4> value> {<br>+ bits<4> Value = value;<br>+}<br>+<br>+def HasV2SubT : SubTarget<0xf>;<br>+def HasV2SubTOnly : SubTarget<0x1>;<br>+def NoV2SubT : SubTarget<0x0>;<br>+def HasV3SubT : SubTarget<0xe>;<br>+def HasV3SubTOnly : SubTarget<0x2>;<br>+def NoV3SubT : SubTarget<0x1>;<br>+def HasV4SubT : SubTarget<0xc>;<br>+def NoV4SubT : SubTarget<0x3>;<br>+def HasV5SubT : SubTarget<0x8>;<br>+def NoV5SubT : SubTarget<0x7>;<br>+<br>+// Addressing modes for load/store instructions<br>+class AddrModeType<bits<4> value> {<br>+ bits<4> Value = value;<br>+}<br>+<br>+def NoAddrMode : AddrModeType<0>; // No addressing mode<br>+def Absolute : AddrModeType<1>; // Absolute addressing mode<br>+def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode<br>+def BaseImmOffset : AddrModeType<3>; // Indirect with offset<br>+def BaseLongOffset : AddrModeType<4>; // Indirect with long offset<br>+def BaseRegOffset : AddrModeType<5>; // Indirect with register offset<br>+<br> //===----------------------------------------------------------------------===//<br> // Intruction Class Declaration +<br> //===----------------------------------------------------------------------===//<br>@@ -55,10 +83,38 @@<br> // Predicated instructions.<br> bits<1> isPredicated = 0;<br> let TSFlags{6} = isPredicated;<br>+ bits<1> isPredicatedNew = 0;<br>+ let TSFlags{7} = isPredicatedNew;<br>+<br>+ // Stores that can be newified.<br>+ bits<1> isNVStorable = 0;<br>+ let TSFlags{8} = isNVStorable;<br><br>- // Dot new value store instructions.<br>+ // New-value store instructions.<br> bits<1> isNVStore = 0;<br>- let TSFlags{8} = isNVStore;<br>+ let TSFlags{9} = isNVStore;<br>+<br>+ // Immediate extender helper fields.<br>+ bits<1> isExtendable = 0;<br>+ let TSFlags{10} = isExtendable; // Insn may be extended.<br>+ bits<1> isExtended = 0;<br>+ let TSFlags{11} = isExtended; // Insn must be extended.<br>+ bits<3> opExtendable = 0;<br>+ let TSFlags{14-12} = opExtendable; // Which operand may be extended.<br>+ bits<1> isExtentSigned = 0;<br>+ let TSFlags{15} = isExtentSigned; // Signed or unsigned range.<br>+ bits<5> opExtentBits = 0;<br>+ let TSFlags{20-16} = opExtentBits; //Number of bits of range before extending.<br>+<br>+ // If an instruction is valid on a subtarget (v2-v5), set the corresponding<br>+ // bit from validSubTargets. v2 is the least significant bit.<br>+ // By default, instruction is valid on all subtargets.<br>+ SubTarget validSubTargets = HasV2SubT;<br>+ let TSFlags{24-21} = validSubTargets.Value;<br>+<br>+ // Addressing mode for load/store instrutions.<br>+ AddrModeType addrMode = NoAddrMode;<br>+ let TSFlags{28-25} = addrMode.Value;<br><br> // Fields used for relation models.<br> string BaseOpcode = "";<br>@@ -66,7 +122,10 @@<br> string PredSense = "";<br> string PNewValue = "";<br> string InputType = ""; // Input is "imm" or "reg" type.<br>- // *** The code above must match HexagonBaseInfo.h ***<br>+ string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.<br>+ string isFloat = "false"; // Set to "true" for the floating-point load/store.<br>+<br>+ // *** Must match MCTargetDesc/HexagonBaseInfo.h ***<br> }<br><br> //===----------------------------------------------------------------------===//<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=167974&r1=167973&r2=167974&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=167974&r1=167973&r2=167974&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Nov 14 14:38:48 2012<br>@@ -26,6 +26,12 @@<br> // ImmRegRel - Filter class used to relate instructions having reg-reg form<br> // with their reg-imm counterparts.<br> class ImmRegRel;<br>+// NewValueRel - Filter class used to relate regular store instructions with<br>+// their new-value store form.<br>+class NewValueRel: PredNewRel;<br>+// NewValueRel - Filter class used to relate load/store instructions having<br>+// different addressing modes with each other.<br>+class AddrModeRel: NewValueRel;<br><br> //===----------------------------------------------------------------------===//<br> // Hexagon Instruction Predicate Definitions.<br>@@ -819,8 +825,6 @@<br> // LD +<br> //===----------------------------------------------------------------------===//<br> ///<br>-/// Make sure that in post increment load, the first operand is always the post<br>-/// increment operand.<br> ///<br> // Load doubleword.<br> let isPredicable = 1 in<br>@@ -851,12 +855,65 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memd($src1++#$offset)",<br>+//===----------------------------------------------------------------------===//<br>+// Post increment load<br>+// Make sure that in post increment load, the first operand is always the post<br>+// increment operand.<br>+//===----------------------------------------------------------------------===//<br>+<br>+multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,<br>+ bit isNot, bit isPredNew> {<br>+ let PNewValue = #!if(isPredNew, "new", "") in<br>+ def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),<br>+ (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),<br>+ #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",<br>+ ") ")#"$dst = "#mnemonic#"($src2++#$offset)",<br> [],<br>- "$src1 = $dst2">;<br>+ "$src2 = $dst2">;<br>+}<br>+<br>+multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,<br>+ Operand ImmOp, bit PredNot> {<br>+ let PredSense = #!if(PredNot, "false", "true") in {<br>+ defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;<br>+ // Predicate new<br>+ let Predicates = [HasV4T], validSubTargets = HasV4SubT in<br>+ defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;<br>+ }<br>+}<br>+<br>+multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,<br>+ Operand ImmOp> {<br>+<br>+ let BaseOpcode = "POST_"#BaseOp in {<br>+ let isPredicable = 1 in<br>+ def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),<br>+ (ins IntRegs:$src1, ImmOp:$offset),<br>+ "$dst = "#mnemonic#"($src1++#$offset)",<br>+ [],<br>+ "$src1 = $dst2">;<br>+<br>+ let isPredicated = 1 in {<br>+ defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;<br>+ defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;<br>+ }<br>+ }<br>+}<br>+<br>+let hasCtrlDep = 1, neverHasSideEffects = 1 in {<br>+ defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,<br>+ PredNewRel;<br>+ defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,<br>+ PredNewRel;<br>+ defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,<br>+ PredNewRel;<br>+ defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,<br>+ PredNewRel;<br>+ defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,<br>+ PredNewRel;<br>+ defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,<br>+ PredNewRel;<br>+}<br><br> // Load doubleword conditionally.<br> let neverHasSideEffects = 1, isPredicated = 1 in<br>@@ -884,20 +941,6 @@<br> "if (!$src1) $dst = memd($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),<br>- "if ($src1) $dst1 = memd($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrid_cNotPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),<br>- "if (!$src1) $dst1 = memd($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br>@@ -969,13 +1012,6 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDrib : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memb($src1++#$offset)",<br>- [],<br>- "$src1 = $dst2">;<br>-<br> // Load byte conditionally.<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDrib_cPt : LDInst2<(outs IntRegs:$dst),<br>@@ -1001,20 +1037,6 @@<br> "if (!$src1) $dst = memb($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrib_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if ($src1) $dst1 = memb($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrib_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if (!$src1) $dst1 = memb($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br>@@ -1083,13 +1105,6 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDrih : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memh($src1++#$offset)",<br>- [],<br>- "$src1 = $dst2">;<br>-<br> // Load halfword conditionally.<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDrih_cPt : LDInst2<(outs IntRegs:$dst),<br>@@ -1115,20 +1130,6 @@<br> "if (!$src1) $dst = memh($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrih_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if ($src1) $dst1 = memh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrih_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if (!$src1) $dst1 = memh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br>@@ -1182,13 +1183,6 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDriub : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memub($src1++#$offset)",<br>- [],<br>- "$src1 = $dst2">;<br>-<br> // Load unsigned byte conditionally.<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDriub_cPt : LDInst2<(outs IntRegs:$dst),<br>@@ -1214,20 +1208,6 @@<br> "if (!$src1) $dst = memub($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriub_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if ($src1) $dst1 = memub($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriub_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if (!$src1) $dst1 = memub($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br>@@ -1275,13 +1255,6 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDriuh : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memuh($src1++#$offset)",<br>- [],<br>- "$src1 = $dst2">;<br>-<br> // Load unsigned halfword conditionally.<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),<br>@@ -1307,20 +1280,6 @@<br> "if (!$src1) $dst = memuh($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriuh_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if ($src1) $dst1 = memuh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriuh_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if (!$src1) $dst1 = memuh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br>@@ -1381,13 +1340,6 @@<br> []>,<br> Requires<[NoV4T]>;<br><br>-let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in<br>-def POST_LDriw : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),<br>- (ins IntRegs:$src1, s4Imm:$offset),<br>- "$dst = memw($src1++#$offset)",<br>- [],<br>- "$src1 = $dst2">;<br>-<br> // Load word conditionally.<br><br> let neverHasSideEffects = 1, isPredicated = 1 in<br>@@ -1414,20 +1366,6 @@<br> "if (!$src1) $dst = memw($src2+#$src3)",<br> []>;<br><br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriw_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),<br>- "if ($src1) $dst1 = memw($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriw_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),<br>- "if (!$src1) $dst1 = memw($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">;<br>-<br> let neverHasSideEffects = 1, isPredicated = 1 in<br> def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),<br> (ins PredRegs:$src1, MEMri:$addr),<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=167974&r1=167973&r2=167974&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=167974&r1=167973&r2=167974&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Wed Nov 14 14:38:48 2012<br>@@ -1002,108 +1002,6 @@<br> []>,<br> Requires<[HasV4T]>;<br><br>-// Rd=memw(Rt<<#u2+#U6)<br>-<br>-<br>-// Post-inc Load, Predicated, Dot new<br>-<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrid_cdnPt_V4 : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),<br>- "if ($src1.new) $dst1 = memd($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrid_cdnNotPt_V4 : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),<br>- "if (!$src1.new) $dst1 = memd($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrib_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if ($src1.new) $dst1 = memb($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrib_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if (!$src1.new) $dst1 = memb($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrih_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if ($src1.new) $dst1 = memh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDrih_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if (!$src1.new) $dst1 = memh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriub_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if ($src1.new) $dst1 = memub($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriub_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),<br>- "if (!$src1.new) $dst1 = memub($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriuh_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if ($src1.new) $dst1 = memuh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriuh_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),<br>- "if (!$src1.new) $dst1 = memuh($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriw_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),<br>- "if ($src1.new) $dst1 = memw($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br>-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>-def POST_LDriw_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),<br>- (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),<br>- "if (!$src1.new) $dst1 = memw($src2++#$src3)",<br>- [],<br>- "$src2 = $dst2">,<br>- Requires<[HasV4T]>;<br>-<br> /// Load from global offset<br><br> let isPredicable = 1, neverHasSideEffects = 1 in<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=167974&r1=167973&r2=167974&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=167974&r1=167973&r2=167974&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Wed Nov 14 14:38:48 2012<br>@@ -43,7 +43,27 @@<br> TypeMARKER = 31 // Such as end of a HW loop.<br> };<br><br>+ enum SubTarget {<br>+ HasV2SubT = 0xf,<br>+ HasV2SubTOnly = 0x1,<br>+ NoV2SubT = 0x0,<br>+ HasV3SubT = 0xe,<br>+ HasV3SubTOnly = 0x2,<br>+ NoV3SubT = 0x1,<br>+ HasV4SubT = 0xc,<br>+ NoV4SubT = 0x3,<br>+ HasV5SubT = 0x8,<br>+ NoV5SubT = 0x7<br>+ };<br><br>+ enum AddrMode {<br>+ NoAddrMode = 0, // No addressing mode<br>+ Absolute = 1, // Absolute addressing mode<br>+ AbsoluteSet = 2, // Absolute set addressing mode<br>+ BaseImmOffset = 3, // Indirect with offset<br>+ BaseLongOffset = 4, // Indirect with long offset<br>+ BaseRegOffset = 5 // Indirect with register offset<br>+ };<br><br> // MCInstrDesc TSFlags<br> // *** Must match HexagonInstrFormat*.td ***<br>@@ -58,8 +78,47 @@<br><br> // Predicated instructions.<br> PredicatedPos = 6,<br>- PredicatedMask = 0x1<br>- };<br>+ PredicatedMask = 0x1,<br>+ PredicatedNewPos = 7,<br>+ PredicatedNewMask = 0x1,<br>+<br>+ // Stores that can be newified.<br>+ mayNVStorePos = 8,<br>+ mayNVStoreMask = 0x1,<br>+<br>+ // Dot new value store instructions.<br>+ NVStorePos = 9,<br>+ NVStoreMask = 0x1,<br>+<br>+ // Extendable insns.<br>+ ExtendablePos = 10,<br>+ ExtendableMask = 0x1,<br>+<br>+ // Insns must be extended.<br>+ ExtendedPos = 11,<br>+ ExtendedMask = 0x1,<br>+<br>+ // Which operand may be extended.<br>+ ExtendableOpPos = 12,<br>+ ExtendableOpMask = 0x7,<br>+<br>+ // Signed or unsigned range.<br>+ ExtentSignedPos = 15,<br>+ ExtentSignedMask = 0x1,<br>+<br>+ // Number of bits of range before extending operand.<br>+ ExtentBitsPos = 16,<br>+ ExtentBitsMask = 0x1f,<br>+<br>+ // Valid subtargets<br>+ validSubTargetPos = 21,<br>+ validSubTargetMask = 0xf,<br>+<br>+ // Addressing mode for load/store instructions<br>+ AddrModePos = 25,<br>+ AddrModeMask = 0xf<br>+<br>+ };<br><br> // *** The code above must match HexagonInstrFormat*.td *** //<br><br><br>Added: llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll?rev=167974&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll?rev=167974&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll (added)<br>+++ llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll Wed Nov 14 14:38:48 2012<br>@@ -0,0 +1,29 @@<br>+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s<br>+<br>+; Check that post-increment load instructions are being generated.<br>+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}})<br>+<br>+define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {<br>+entry:<br>+ br label %for.body<br>+<br>+for.body:<br>+ %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]<br>+ %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]<br>+ %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]<br>+ %sum.03 = phi i32 [ 0, %entry ], [ %add2, %for.body ]<br>+ %0 = load i32* %arrayidx.phi, align 4<br>+ %1 = load i16* %arrayidx1.phi, align 2<br>+ %conv = sext i16 %1 to i32<br>+ %add = add i32 %0, %sum.03<br>+ %add2 = add i32 %add, %conv<br>+ %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1<br>+ %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1<br>+ %lsr.iv.next = add i32 %lsr.iv, -1<br>+ %exitcond = icmp eq i32 %lsr.iv.next, 0<br>+ br i1 %exitcond, label %for.end, label %for.body<br>+<br>+for.end:<br>+ ret i32 %add2<br>+}<br>+<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p></div></div></div></div><p class=MsoNormal><o:p> </o:p></p></div></div></div></body></html>