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<p class="MsoNormal">Can you add a comment in the source on why this check is needed, other than that it looks fine to me.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Micah<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu]
<b>On Behalf Of </b>Gurd, Preston<br>
<b>Sent:</b> Friday, October 26, 2012 3:27 PM<br>
<b>To:</b> llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> [llvm-commits] [PATCH][Review Requested] Fix incorrect scheduling of inline assembly referencing memory<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Here is a patch which fixes the problem with the Post RA scheduler generating an incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing
the scheduler to always assume that any inline assembly code instruction could touch memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This should fix PR13504.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The patch also includes a test case.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Please review!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">--<o:p></o:p></p>
<p class="MsoNormal">Preston Gurd <<a href="mailto:preston.gurd@intel.com">preston.gurd@intel.com</a>><o:p></o:p></p>
<p class="MsoNormal"> Intel Waterloo<o:p></o:p></p>
<p class="MsoNormal"> SSG/DPD/ECDL/DMP<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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