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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='color:#1F497D'>Hi Silviu,<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Thanks for the suggestion. That sounds like another way to fix the issue. We started seeing failures after r163304 that added extra support for vduplane (</span><a href="http://llvm.org/viewvc/llvm-project?view=rev&revision=163304">http://llvm.org/viewvc/llvm-project?view=rev&revision=163304</a>)<span style='color:#1F497D'>. That change was a nice feature and I thought it had just missed a few patterns for going from Q to D vectors.<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Is there a disadvantage to adding these patterns? If I understand correctly, I think the patterns are essentially doing what you suggest, but doing it in the instruction selector itself rather than with code.<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'> <o:p></o:p></span></p><div><p class=MsoNormal><span style='color:#1F497D'>-- </span><span style='color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p></div><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Silviu Baranga [mailto:silbar01@arm.com] <br><b>Sent:</b> Thursday, September 27, 2012 2:02 AM<br><b>To:</b> 'David Peixotto'; James Molloy; llvm-commits@cs.uiuc.edu<br><b>Subject:</b> RE: [llvm-commits] [PATCH] Fix instruction selection for vduplane from v4f32 to v2f32<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>Hi David,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>Wouldn’t it be better to fix the original problem? <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>It seems that the problem is that the BUILD_VECTOR lowering code is creating a VDUPLANE <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>node that takes a v4i32/v4f32 and creates a v2i32/v2f32. It shouldn’t do that. It should extract<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>the D subreg and do a VDUPLANE on that in this case.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>Cheers,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>Silviu<o:p></o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> <a href="mailto:[mailto:llvm-commits-bounces@cs.uiuc.edu]">[mailto:llvm-commits-bounces@cs.uiuc.edu]</a> <b>On Behalf Of </b>David Peixotto<br><b>Sent:</b> 27 September 2012 00:55<br><b>To:</b> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><b>Subject:</b> [llvm-commits] [PATCH] Fix instruction selection for vduplane from v4f32 to v2f32<o:p></o:p></span></p></div></div><p class=MsoNormal><span lang=EN-GB><o:p> </o:p></span></p><p class=MsoPlainText>We are seeing some instruction selection failures for vduplane from larger vectors to smaller vectors. See PR13938: <a href="http://llvm.org/bugs/show_bug.cgi?id=13938">http://llvm.org/bugs/show_bug.cgi?id=13938</a>.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>A patch to fix this issue is attached.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This patch fixes an instruction selection failure for<o:p></o:p></p><p class=MsoNormal>ARMISD::VDUPLANE. The selector was missing patterns for using vdup<o:p></o:p></p><p class=MsoNormal>to initialize a vector when the source vector is a Q-reg and the<o:p></o:p></p><p class=MsoNormal>destination vector is a D-reg. The fix is to add new patterns to<o:p></o:p></p><p class=MsoNormal>allow the selector to properly select this pattern.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p></div></div></div></body></html>