Hi Michael,<div><br></div><div>This change broke our ThreadSanitizer bot. I've reduced this to the following:<br><div><br></div><div><div><div>$ cat atomic.cc </div><div>#include <stdio.h></div><div>int main() {</div>
<div> unsigned long long x = (1ULL << 40) + (1 << 3);</div><div> unsigned long long y = __sync_fetch_and_add(&x, 1);</div><div> printf("%lld %lld\n", x, y);</div><div> int xx = 1 << 20;</div>
<div> int yy = __sync_fetch_and_add(&xx, 1);</div><div> printf("%d %d\n", xx, yy);</div><div> return 0;</div><div>}</div><div>$ clang++ atomic.cc && ./a.out </div><div>1099511627785 8</div><div>1048577 1048576</div>
</div><div><br></div><div>Is it possible that __sync_fetch_and_add for unsigned long long returns the low 32 bits of the changed value?</div><br><div class="gmail_quote">On Fri, Sep 21, 2012 at 7:00 AM, Michael Liao <span dir="ltr"><<a href="mailto:michael.liao@intel.com" target="_blank">michael.liao@intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: hliao<br>
Date: Thu Sep 20 22:00:17 2012<br>
New Revision: <a href="tel:164357" value="+49164357">164357</a><br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=164357&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=164357&view=rev</a><br>
Log:<br>
Revise td of X86 atomic instructions<br>
<br>
- Rewirte most atomic instructions in templates for both better<br>
maintenance and future extensions, such as HLE in TSX.<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrCompiler.td<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=164357&r1=164356&r2=164357&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=164357&r1=164356&r2=164357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 20 22:00:17 2012<br>
@@ -12153,6 +12153,11 @@<br>
BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);<br>
break;<br>
}<br>
+ case X86::ATOMMAX8:<br>
+ case X86::ATOMMIN8:<br>
+ case X86::ATOMUMAX8:<br>
+ case X86::ATOMUMIN8:<br>
+ llvm_unreachable("Not supported yet!");<br>
case X86::ATOMMAX16:<br>
case X86::ATOMMAX32:<br>
case X86::ATOMMAX64:<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=164357&r1=164356&r2=164357&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=164357&r1=164356&r2=164357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Thu Sep 20 22:00:17 2012<br>
@@ -482,125 +482,74 @@<br>
// Atomic Instruction Pseudo Instructions<br>
//===----------------------------------------------------------------------===//<br>
<br>
-// Atomic exchange, and, or, xor<br>
-let usesCustomInserter = 1 in {<br>
+// Pseudo atomic instructions<br>
+<br>
+multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {<br>
+ let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {<br>
+ def #NAME#8 : I<0, Pseudo, (outs GR8:$dst),<br>
+ (ins i8mem:$ptr, GR8:$val),<br>
+ !strconcat(mnemonic, "8 PSEUDO!"), []>;<br>
+ def #NAME#16 : I<0, Pseudo,(outs GR16:$dst),<br>
+ (ins i16mem:$ptr, GR16:$val),<br>
+ !strconcat(mnemonic, "16 PSEUDO!"), []>;<br>
+ def #NAME#32 : I<0, Pseudo, (outs GR32:$dst),<br>
+ (ins i32mem:$ptr, GR32:$val),<br>
+ !strconcat(mnemonic, "32 PSEUDO!"), []>;<br>
+ def #NAME#64 : I<0, Pseudo, (outs GR64:$dst),<br>
+ (ins i64mem:$ptr, GR64:$val),<br>
+ !strconcat(mnemonic, "64 PSEUDO!"), []>;<br>
+ }<br>
+}<br>
<br>
-def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),<br>
- "#ATOMAND8 PSEUDO!",<br>
- [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;<br>
-def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),<br>
- "#ATOMOR8 PSEUDO!",<br>
- [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;<br>
-def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),<br>
- "#ATOMXOR8 PSEUDO!",<br>
- [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;<br>
-def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),<br>
- "#ATOMNAND8 PSEUDO!",<br>
- [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;<br>
-<br>
-def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMAND16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMOR16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMXOR16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMNAND16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMMIN16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMMAX16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMUMIN16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;<br>
-def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),<br>
- "#ATOMUMAX16 PSEUDO!",<br>
- [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;<br>
-<br>
-<br>
-def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMAND32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMOR32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMXOR32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMNAND32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMMIN32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMMAX32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMUMIN32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;<br>
-def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),<br>
- "#ATOMUMAX32 PSEUDO!",<br>
- [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;<br>
-<br>
-<br>
-<br>
-def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMAND64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMOR64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMXOR64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMNAND64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMMIN64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMMAX64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMUMIN64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;<br>
-def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),<br>
- "#ATOMUMAX64 PSEUDO!",<br>
- [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;<br>
+multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {<br>
+ def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),<br>
+ (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;<br>
+ def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),<br>
+ (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;<br>
+ def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),<br>
+ (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;<br>
+ def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),<br>
+ (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;<br>
}<br>
<br>
-let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in {<br>
-def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMAND6432 PSEUDO!", []>;<br>
-def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMOR6432 PSEUDO!", []>;<br>
-def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMXOR6432 PSEUDO!", []>;<br>
-def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMNAND6432 PSEUDO!", []>;<br>
-def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMADD6432 PSEUDO!", []>;<br>
-def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMSUB6432 PSEUDO!", []>;<br>
-def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
- (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
- "#ATOMSWAP6432 PSEUDO!", []>;<br>
+// Atomic exchange, and, or, xor<br>
+defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;<br>
+defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;<br>
+defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;<br>
+defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;<br>
+defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;<br>
+defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;<br>
+defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;<br>
+defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;<br>
+<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;<br>
+defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;<br>
+<br>
+multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {<br>
+ let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in<br>
+ def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),<br>
+ (ins i64mem:$ptr, GR32:$val1, GR32:$val2),<br>
+ !strconcat(mnemonic, "6432 PSEUDO!"), []>;<br>
}<br>
<br>
+defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMAND">;<br>
+defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMOR">;<br>
+defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMXOR">;<br>
+defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMNAND">;<br>
+defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMADD">;<br>
+defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSUB">;<br>
+defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMAX">;<br>
+defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMIN">;<br>
+defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMAX">;<br>
+defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMIN">;<br>
+defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSWAP">;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// Normal-Instructions-With-Lock-Prefix Pseudo Instructions<br>
//===----------------------------------------------------------------------===//<br>
@@ -712,107 +661,125 @@<br>
defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;<br>
<br>
// Optimized codegen when the non-memory output is not used.<br>
+multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,<br>
+ string mnemonic> {<br>
let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {<br>
<br>
-def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),<br>
- "lock\n\t"<br>
- "inc{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
-def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),<br>
- "lock\n\t"<br>
- "inc{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;<br>
-def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),<br>
- "lock\n\t"<br>
- "inc{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
-def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),<br>
- "lock\n\t"<br>
- "inc{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
-<br>
-def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),<br>
- "lock\n\t"<br>
- "dec{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
-def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),<br>
- "lock\n\t"<br>
- "dec{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;<br>
-def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),<br>
- "lock\n\t"<br>
- "dec{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
-def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),<br>
- "lock\n\t"<br>
- "dec{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;<br>
+def #NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),<br>
+ !strconcat("lock\n\t", mnemonic, "{b}\t$dst"),<br>
+ [], IIC_UNARY_MEM>, LOCK;<br>
+def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),<br>
+ !strconcat("lock\n\t", mnemonic, "{w}\t$dst"),<br>
+ [], IIC_UNARY_MEM>, OpSize, LOCK;<br>
+def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),<br>
+ !strconcat("lock\n\t", mnemonic, "{l}\t$dst"),<br>
+ [], IIC_UNARY_MEM>, LOCK;<br>
+def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),<br>
+ !strconcat("lock\n\t", mnemonic, "{q}\t$dst"),<br>
+ [], IIC_UNARY_MEM>, LOCK;<br>
+}<br>
}<br>
<br>
-// Atomic compare and swap.<br>
-let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],<br>
- isCodeGenOnly = 1 in<br>
-def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),<br>
- "lock\n\t"<br>
- "cmpxchg8b\t$ptr",<br>
- [(X86cas8 addr:$ptr)], IIC_CMPX_LOCK_8B>, TB, LOCK;<br>
+defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;<br>
+defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;<br>
<br>
-let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],<br>
- isCodeGenOnly = 1 in<br>
-def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),<br>
- "lock\n\t"<br>
- "cmpxchg16b\t$ptr",<br>
- [(X86cas16 addr:$ptr)], IIC_CMPX_LOCK_16B>, TB, LOCK,<br>
- Requires<[HasCmpxchg16b]>;<br>
-<br>
-let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {<br>
-def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),<br>
- "lock\n\t"<br>
- "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",<br>
- [(X86cas addr:$ptr, GR8:$swap, 1)], IIC_CMPX_LOCK_8>, TB, LOCK;<br>
+// Atomic compare and swap.<br>
+multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,<br>
+ SDPatternOperator frag, X86MemOperand x86memop,<br>
+ InstrItinClass itin> {<br>
+let isCodeGenOnly = 1 in {<br>
+ def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr),<br>
+ !strconcat("lock\n\t", mnemonic, "\t$ptr"),<br>
+ [(frag addr:$ptr)], itin>, TB, LOCK;<br>
+}<br>
}<br>
<br>
-let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {<br>
-def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),<br>
- "lock\n\t"<br>
- "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",<br>
- [(X86cas addr:$ptr, GR16:$swap, 2)], IIC_CMPX_LOCK>, TB, OpSize, LOCK;<br>
+multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,<br>
+ string mnemonic, SDPatternOperator frag,<br>
+ InstrItinClass itin8, InstrItinClass itin> {<br>
+let isCodeGenOnly = 1 in {<br>
+ let Defs = [AL, EFLAGS], Uses = [AL] in<br>
+ def #NAME#8 : I<Opc, Form, (outs), (ins i8mem:$ptr, GR8:$swap),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{b}\t{$swap, $ptr|$ptr, $swap}"),<br>
+ [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;<br>
+ let Defs = [AX, EFLAGS], Uses = [AX] in<br>
+ def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{w}\t{$swap, $ptr|$ptr, $swap}"),<br>
+ [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;<br>
+ let Defs = [EAX, EFLAGS], Uses = [EAX] in<br>
+ def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{l}\t{$swap, $ptr|$ptr, $swap}"),<br>
+ [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;<br>
+ let Defs = [RAX, EFLAGS], Uses = [RAX] in<br>
+ def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{q}\t{$swap, $ptr|$ptr, $swap}"),<br>
+ [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;<br>
+}<br>
}<br>
<br>
-let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {<br>
-def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),<br>
- "lock\n\t"<br>
- "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",<br>
- [(X86cas addr:$ptr, GR32:$swap, 4)], IIC_CMPX_LOCK>, TB, LOCK;<br>
+let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {<br>
+defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",<br>
+ X86cas8, i64mem,<br>
+ IIC_CMPX_LOCK_8B>;<br>
}<br>
<br>
-let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {<br>
-def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),<br>
- "lock\n\t"<br>
- "cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}",<br>
- [(X86cas addr:$ptr, GR64:$swap, 8)], IIC_CMPX_LOCK>, TB, LOCK;<br>
+let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],<br>
+ Predicates = [HasCmpxchg16b] in {<br>
+defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",<br>
+ X86cas16, i128mem,<br>
+ IIC_CMPX_LOCK_16B>, REX_W;<br>
}<br>
<br>
+defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",<br>
+ X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;<br>
+<br>
// Atomic exchange and add<br>
-let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {<br>
-def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),<br>
- "lock\n\t"<br>
- "xadd{b}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))],<br>
- IIC_XADD_LOCK_MEM8>,<br>
- TB, LOCK;<br>
-def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),<br>
- "lock\n\t"<br>
- "xadd{w}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))],<br>
- IIC_XADD_LOCK_MEM>,<br>
- TB, OpSize, LOCK;<br>
-def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),<br>
- "lock\n\t"<br>
- "xadd{l}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))],<br>
- IIC_XADD_LOCK_MEM>,<br>
- TB, LOCK;<br>
-def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),<br>
- "lock\n\t"<br>
- "xadd{q}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))],<br>
- IIC_XADD_LOCK_MEM>,<br>
- TB, LOCK;<br>
+multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,<br>
+ string frag,<br>
+ InstrItinClass itin8, InstrItinClass itin> {<br>
+ let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {<br>
+ def #NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),<br>
+ (ins GR8:$val, i8mem:$ptr),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{b}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set GR8:$dst,<br>
+ (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],<br>
+ itin8>;<br>
+ def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),<br>
+ (ins GR16:$val, i16mem:$ptr),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{w}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR16:$dst,<br>
+ (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],<br>
+ itin>;<br>
+ def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),<br>
+ (ins GR32:$val, i32mem:$ptr),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{l}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR32:$dst,<br>
+ (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],<br>
+ itin>;<br>
+ def #NAME#64 : I<opc, MRMSrcMem, (outs GR64:$dst),<br>
+ (ins GR64:$val, i64mem:$ptr),<br>
+ !strconcat("lock\n\t", mnemonic,<br>
+ "{q}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR64:$dst,<br>
+ (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],<br>
+ itin>;<br>
+ }<br>
}<br>
<br>
+defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",<br>
+ IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,<br>
+ TB, LOCK;<br>
+<br>
def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),<br>
"#ACQUIRE_MOV PSEUDO!",<br>
[(set GR8:$dst, (atomic_load_8 addr:$src))]>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=164357&r1=164356&r2=164357&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=164357&r1=164356&r2=164357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Sep 20 22:00:17 2012<br>
@@ -1266,28 +1266,46 @@<br>
// Atomic support<br>
//<br>
<br>
-<br>
// Atomic swap. These are just normal xchg instructions. But since a memory<br>
// operand is referenced, the atomicity is ensured.<br>
-let Constraints = "$val = $dst" in {<br>
-def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),<br>
- "xchg{b}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))],<br>
- IIC_XCHG_MEM>;<br>
-def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),<br>
- "xchg{w}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))],<br>
- IIC_XCHG_MEM>,<br>
- OpSize;<br>
-def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),<br>
- "xchg{l}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))],<br>
- IIC_XCHG_MEM>;<br>
-def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),<br>
- "xchg{q}\t{$val, $ptr|$ptr, $val}",<br>
- [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))],<br>
- IIC_XCHG_MEM>;<br>
+multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,<br>
+ InstrItinClass itin> {<br>
+ let Constraints = "$val = $dst" in {<br>
+ def #NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),<br>
+ (ins GR8:$val, i8mem:$ptr),<br>
+ !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR8:$dst,<br>
+ (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],<br>
+ itin>;<br>
+ def #NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),<br>
+ (ins GR16:$val, i16mem:$ptr),<br>
+ !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR16:$dst,<br>
+ (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],<br>
+ itin>, OpSize;<br>
+ def #NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),<br>
+ (ins GR32:$val, i32mem:$ptr),<br>
+ !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR32:$dst,<br>
+ (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],<br>
+ itin>;<br>
+ def #NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),<br>
+ (ins GR64:$val, i64mem:$ptr),<br>
+ !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),<br>
+ [(set<br>
+ GR64:$dst,<br>
+ (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],<br>
+ itin>;<br>
+ }<br>
+}<br>
<br>
+defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;<br>
+<br>
+// Swap between registers.<br>
+let Constraints = "$val = $dst" in {<br>
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),<br>
"xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;<br>
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),<br>
@@ -1298,6 +1316,7 @@<br>
"xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;<br>
}<br>
<br>
+// Swap between EAX and other registers.<br>
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),<br>
"xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;<br>
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Alexey Samsonov, MSK</div><br>
</div></div>