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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Just a note to say that this commit is causing 3 tests in the regression suite to fail on ARM/Linux<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>test/CodeGen/ARM/twoaddrinstr.ll<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>test/CodeGen/ARM/reg_sequence.ll<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>test/CodeGen/ARM/vbsl-constant.ll<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I'm haven't yet had time to look into them in any detail and see if it's a test that's no longer valid or it's actually producing wrong code. (It all seems to come down to 64 not 32 bit instructions, which the changelog suggests is intended and the test is wrong:<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>/home/buildslave/buildslave/runtests/llvm/test/CodeGen/ARM/twoaddrinstr.ll:7:10: error: expected string not found in input<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>; CHECK: vld1.32<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> ^<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><stdin>:15:10: note: scanning from here<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>PR13378: @ @PR13378<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> ^<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><stdin>:18:2: note: possible intended match here<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> vld1.64 {d0, d1}, [r0]<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>)<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Regards,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>David Tweed<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Evan Cheng<br><b>Sent:</b> 18 September 2012 02:48<br><b>To:</b> David Peixotto<br><b>Cc:</b> llvm-commits@cs.uiuc.edu<br><b>Subject:</b> Re: [llvm-commits] [PATCH] Use vld1/vst1 for unaligned load/store<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>r164089. Thanks.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Evan<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Sep 17, 2012, at 11:11 AM, Evan Cheng <<a href="mailto:evan.cheng@apple.com">evan.cheng@apple.com</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><p class=MsoNormal>Hi David,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks for working on this. This is a big omission that I was planning to look at. It's good you got to it first. Some comments though:<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><p class=MsoNormal> bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { <o:p></o:p></p></div><div><p class=MsoNormal>- if (!Subtarget->allowsUnalignedMem()) <o:p></o:p></p></div><div><p class=MsoNormal>- return false; <o:p></o:p></p></div><div><p class=MsoNormal>+ // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus <o:p></o:p></p></div><div><p class=MsoNormal>+ bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); <o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><p class=MsoNormal> switch (VT.getSimpleVT().SimpleTy) { <o:p></o:p></p></div><div><p class=MsoNormal> default: <o:p></o:p></p></div><div><p class=MsoNormal>@@ -9034,10 +9034,15 @@ bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {<o:p></o:p></p></div><div><p class=MsoNormal> case MVT::i8: <o:p></o:p></p></div><div><p class=MsoNormal> case MVT::i16: <o:p></o:p></p></div><div><p class=MsoNormal> case MVT::i32: <o:p></o:p></p></div><div><p class=MsoNormal>- return true; <o:p></o:p></p></div><div><p class=MsoNormal>+ // Unaligned access can use (for example) LRDB, LRDH, LDR <o:p></o:p></p></div><div><p class=MsoNormal>+ return AllowsUnaligned; <o:p></o:p></p></div><div><p class=MsoNormal> case MVT::f64: <o:p></o:p></p></div><div><p class=MsoNormal>- return Subtarget->hasNEON(); <o:p></o:p></p></div><div><p class=MsoNormal>- // FIXME: VLD1 etc with standard alignment is legal. <o:p></o:p></p></div><div><p class=MsoNormal>+ case MVT::v2f64: <o:p></o:p></p></div><div><p class=MsoNormal>+ // For any little-endian targets with neon, we can support unaligned ld/st <o:p></o:p></p></div><div><p class=MsoNormal>+ // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8. <o:p></o:p></p></div><div><p class=MsoNormal>+ // A big-endian target may also explictly support unaligned accesses <o:p></o:p></p></div><div><p class=MsoNormal>+ return Subtarget->hasNEON() && <o:p></o:p></p></div><div><p class=MsoNormal>+ (getTargetData()->isLittleEndian() || AllowsUnaligned); <o:p></o:p></p></div><div><p class=MsoNormal> } <o:p></o:p></p></div><div><p class=MsoNormal> } <o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>This part is not quite right:<o:p></o:p></p></div><div><div><p class=MsoNormal>+ return Subtarget->hasNEON() && <o:p></o:p></p></div><div><p class=MsoNormal>+ (getTargetData()->isLittleEndian() || AllowsUnaligned); <o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>vld1 / vst1 requires alignment of element size. If not, then it's a fault unless SCTLR.A is 1. This should not require true for all little endian cpus with NEON. It should still be controlled by the subtarget feature.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I'll fix up your patch and commit it for you. Thanks.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Evan<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><p class=MsoNormal>On Sep 13, 2012, at 5:53 PM, David Peixotto <<a href="mailto:dpeixott@codeaurora.org">dpeixott@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>This patch is the result of a discussion of unaligned vector loads/store on llvmdev:<span class=apple-converted-space> </span><a href="http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-September/053082.html"><span style='color:purple'>http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-September/053082.html</span></a>.<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The vld1 and vst1 variants in armv7 neon only require memory<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>alignment to the element size of the vector. Because of this<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>property, we can use a vld1.8 and vst1.8 to load/store f64 and v2f64<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>vectors to unaligned addresses on little-endian targets. This should<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>be faster than the target-independent codegen lowering that does an<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>aligned load/store to the stack and unaligned load/store of each<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>element of the vector.<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>This patch includes two changes:<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> 1. Add new patterns for selecting vld1/vst1 for byte and half-word<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> aligned vector stores for v2f64 vectors.<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> 2. Allow unaligned load/store using vld1/vst1 for little-endian<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> arm targets that support NEON. The vld1/vst1 instructions will<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> be used to load/store f64 and v2f64 types aligned along byte<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> and half-word memory accesses.<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><p class=MsoNormal><span lang=EN-US style='font-size:13.5pt;font-family:"Helvetica","sans-serif"'><0001-Use-vld1-vst1-for-unaligned-load-store.patch>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:purple'>llvm-commits@cs.uiuc.edu</span></a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits"><span style='color:purple'>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</span></a><o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p></div></div><p class=MsoNormal>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>