<html><body><div style="color:#000; background-color:#fff; font-family:arial, helvetica, sans-serif;font-size:10pt">Are we just trying to save time during emission or is there another reason for making something manual that used to be automatic? It is definitely more error prone (as your commit already indicates). Would it make sense to keep the code for DEBUG, so that it can assert if there is an inconsistency.<br><br>- Jan<br><div><span> <br></span></div><div><br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; margin-top: 5px; padding-left: 5px;">  <div style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"> <div style="font-family: times new roman, new york, times, serif; font-size: 12pt;"> <div dir="ltr"> <font size="2" face="Arial"> <hr size="1">  <b><span style="font-weight:bold;">From:</span></b> Craig Topper <craig.topper@gmail.com><br> <b><span style="font-weight: bold;">To:</span></b>

 llvm-commits@cs.uiuc.edu <br> <b><span style="font-weight: bold;">Sent:</span></b> Wednesday, September 19, 2012 2:37 AM<br> <b><span style="font-weight: bold;">Subject:</span></b> [llvm-commits] [llvm] r164204 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrSSE.td utils/TableGen/X86RecognizableInstr.cpp utils/TableGen/X86RecognizableInstr.h<br> </font> </div> <br>

Author: ctopper Date: Wed Sep 19 01:37:45 2012 New Revision: 164204 URL: http://llvm.org/viewvc/llvm-project?rev=164204&view=rev Log: Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. Modified:     llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp     llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp     llvm/trunk/lib/Target/X86/X86InstrSSE.td     llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp     llvm/trunk/utils/TableGen/X86RecognizableInstr.h Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp URL:

 http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=164204&r1=164203&r2=164204&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Sep 19 01:37:45 2012<br>@@ -560,15 +560,6 @@<br>   }<br> <br> <br>-  // Set the vector length to 256-bit if YMM0-YMM15 is used<br>-  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {<br>-    if (!MI.getOperand(i).isReg())<br>-      continue;<br>-    unsigned SrcReg = MI.getOperand(i).getReg();<br>-    if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)<br>-      VEX_L = 1;<br>-  }<br>-<br>   // Classify VEX_B, VEX_4V, VEX_R, VEX_X<br>   unsigned NumOps =

 Desc.getNumOperands();<br>   unsigned CurOp = 0;<br><br>Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=164204&r1=164203&r2=164204&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Sep 19 01:37:45 2012<br>@@ -921,17 +921,6 @@<br>   }<br> <br> <br>-  // Set the vector length to 256-bit if YMM0-YMM15 is used<br>-  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {<br>-    if (!MI.getOperand(i).isReg())<br>-      continue;<br>-    if (MI.getOperand(i).isImplicit())<br>-      continue;<br>-    unsigned SrcReg = MI.getOperand(i).getReg();<br>-    if (SrcReg >= X86::YMM0 && SrcReg <=

 X86::YMM15)<br>-      VEX_L = 1;<br>-  }<br>-<br>   // Classify VEX_B, VEX_4V, VEX_R, VEX_X<br>   unsigned NumOps = Desc->getNumOperands();<br>   unsigned CurOp = 0;<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=164204&r1=164203&r2=164204&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 19 01:37:45 2012<br>@@ -2614,11 +2614,11 @@<br>              OpSize, VEX;<br>   def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),<br>              "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,<br>-            

 SSEPackedSingle>, TB, VEX;<br>+             SSEPackedSingle>, TB, VEX, VEX_L;<br>   def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),<br>              "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,<br>              SSEPackedDouble>, TB,<br>-             OpSize, VEX;<br>+             OpSize, VEX, VEX_L;<br> }<br> <br> defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",<br><br>Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=164204&r1=164203&r2=164204&view=diff<br>==============================================================================<br>---

 llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Wed Sep 19 01:37:45 2012<br>@@ -244,7 +244,7 @@<br>   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||<br>                      (Name.find("CRC32") != Name.npos);<br>   HasFROperands    = hasFROperands();<br>-  HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");<br>+  HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");<br> <br>   // Check for 64-bit inst which does not require REX<br>   Is32Bit = false;<br>@@ -479,20 +479,6 @@<br>   return false;<br> }<br> <br>-bool RecognizableInstr::has256BitOperands() const {<br>-  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;<br>-  unsigned numOperands =

 OperandList.size();<br>-<br>-  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {<br>-    const std::string &recName = OperandList[operandIndex].Rec->getName();<br>-<br>-    if (!recName.compare("VR256")) {<br>-      return true;<br>-    }<br>-  }<br>-  return false;<br>-}<br>-<br> void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,<br>                                       unsigned &physicalOperandIndex,<br>                                       unsigned &numPhysicalOperands,<br><br>Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.h<br>URL: <a

 href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.h?rev=164204&r1=164203&r2=164204&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.h?rev=164204&r1=164203&r2=164204&view=diff</a><br>==============================================================================<br>--- llvm/trunk/utils/TableGen/X86RecognizableInstr.h (original)<br>+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.h Wed Sep 19 01:37:45 2012<br>@@ -127,10 +127,7 @@<br> <br>   /// hasFROperands - Returns true if any operand is a FR operand.<br>   bool hasFROperands() const;<br>-  <br>-  /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.<br>-  bool has256BitOperands() const;<br>-  <br>+<br>   /// typeFromString - Translates an operand type from the string provided in<br>   ///   the LLVM tables to

 an OperandType for use in the operand specifier.<br>   ///<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a ymailto="mailto:llvm-commits@cs.uiuc.edu" href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br><br><br> </div> </div> </blockquote></div>   </div></body></html>