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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoPlainText>Hi Bill,<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Thanks for the reviewing.<o:p></o:p></p><p class=MsoPlainText style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>Regarding parameter passing<o:p></o:p></p><p class=MsoPlainText>Actually, my first version was passing reference. Later on, I changed it to pass pointer since I can use NULL as the default parameter and thus minimize changes to existing code. Using reference, I have to define a overloaded version that calls the existing version in TargetLower.h as the default implementation, and then override it in ARMISelLowering with my implementation. I can switch to passing reference in my next patch.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>Regarding skipping R10 and comparing reg, I should add parenthesis. My intention is :<o:p></o:p></p><p class=MsoPlainText> Reg != (Subtarget->isThumb() ? ARM::R6 : ARM::R10 My current code was ambiguous and probably wrong. I will fix it. <o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>I will check the find() and tGRPRegclass issue.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>Regarding the return: <o:p></o:p></p><p class=MsoPlainText>when it can't find any available register, it returns "RCPair(0U, NULL);". This is expected behavior. I tested it by occupying almost all the GRPs, and in this case, Clang will return an error nicely:<o:p></o:p></p><p class=MsoPlainText>error: couldn't allocate input reg for constraint 'r'<o:p></o:p></p><p class=MsoPlainText> __asm__ __volatile__("@ atomic64_set\n" <o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Again, thank you, Bill, for your comments and reviewing.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Thanks,<o:p></o:p></p><p class=MsoPlainText>Weiming<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>-----Original Message-----<br>From: Bill Wendling [mailto:wendling@apple.com] <br>Sent: Monday, September 17, 2012 3:03 PM<br>To: Weiming Zhao<br>Cc: llvm-commits@cs.uiuc.edu<br>Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM</p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Hi Weiming,<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>One thing I noticed in your patch, you're passing around a SmallVector as a pointer. Why are you doing that? Instead, you should just pass it by reference:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText> getRegForInlineAsmConstraint(const std::string &Constraint,<o:p></o:p></p><p class=MsoPlainText> EVT VT,<o:p></o:p></p><p class=MsoPlainText> SmallVectorImpl<unsigned> &AssignedPhyRegs) const;<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>etc. It doesn't make sense to have it be a pointer since you're not testing to make sure it's not NULL before you're dereferencing it.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Also, this logic is weird:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ if (VT.getSizeInBits() == 64 && AssignedPhyRegs) {<o:p></o:p></p><p class=MsoPlainText>+ SmallVectorImpl<unsigned>::iterator First = AssignedPhyRegs->begin(),<o:p></o:p></p><p class=MsoPlainText>+ Last = AssignedPhyRegs->end();<o:p></o:p></p><p class=MsoPlainText>+ // The valid registers for ldrexd/strexd is r0-r13 for ARM. But we skip<o:p></o:p></p><p class=MsoPlainText>+ // the pairs using FP(r7/r11 for T1/ARM) and SP(r13) for safety.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>This comment is misleading. We're not skipping R11 for ARM because you have 'Reg <= ARM::R10', which may choose 'R10/R11'.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ for (unsigned Reg = ARM::R0; Reg <= ARM::R10 &&<o:p></o:p></p><p class=MsoPlainText>+ Reg != Subtarget->isThumb() ? ARM::R6 : ARM::R10; Reg += 2)<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Why are you comparing 'Reg', an unsigned, to 'Subtarget->isThumb()', a bool?<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ if (std::find(First, Last, Reg) == Last &&<o:p></o:p></p><p class=MsoPlainText>+ std::find(First, Last, Reg + 1) == Last)<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>This is expensive. Is there another way of doing this without the find? Like maybe creating a bit vector of assigned physregs and then looking at that? (Just for an example...you can come up with your own idea.)<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ return RCPair(Reg, &ARM::GPRRegClass);<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>I think that in Thumb mode, you want ARM::tGPRRegClass instead of ARM::GPRRegClass. (Can anyone confirm this?)<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ return RCPair(0U, NULL);<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Hork? Is this the correct action here? What does this do exactly?<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>+ }<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>-bw<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>On Sep 17, 2012, at 2:32 PM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org"><span style='color:windowtext;text-decoration:none'>weimingz@codeaurora.org</span></a>> wrote:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>> Ping…<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> From: Weiming Zhao <a href="mailto:[mailto:weimingz@codeaurora.org]"><span style='color:windowtext;text-decoration:none'>[mailto:weimingz@codeaurora.org]</span></a> <o:p></o:p></p><p class=MsoPlainText>> Sent: Wednesday, September 12, 2012 10:21 AM<o:p></o:p></p><p class=MsoPlainText>> To: <a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:windowtext;text-decoration:none'>llvm-commits@cs.uiuc.edu</span></a><o:p></o:p></p><p class=MsoPlainText>> Subject: Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Hi,<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Attached is the patch for fixing the long long data passing to inline asm for ARM.<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Since current LLVM has no support for paired GPR reg class for 64-bit data, we follow the same practice as ldrexd/strexd instincs (ARMTargetLowering::EmitAtomicBinary64). That is, we hard code the physical registers.<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> However, since inline asm may has some physical registers specified by programmers, we cannot simply hard code R2/R3 as those intrincs do.<o:p></o:p></p><p class=MsoPlainText>> So, we have to add a variable “AssignedPhyRegs” to track those already specified physical regs of that inline ASM and thus avoid them during assigning.<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Please help to review the patch.<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Thanks,<o:p></o:p></p><p class=MsoPlainText>> Weiming<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<o:p></o:p></p><p class=MsoPlainText>> <o:p></o:p></p><p class=MsoPlainText>> <0001-Bug-13622-Fix-paired-register-for-inline-asm-with-64.patch>_______________________________________________<o:p></o:p></p><p class=MsoPlainText>> llvm-commits mailing list<o:p></o:p></p><p class=MsoPlainText>> <a href="mailto:llvm-commits@cs.uiuc.edu"><span style='color:windowtext;text-decoration:none'>llvm-commits@cs.uiuc.edu</span></a><o:p></o:p></p><p class=MsoPlainText>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits"><span style='color:windowtext;text-decoration:none'>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</span></a><o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p></div></body></html>