Index: test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
===================================================================
--- test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt	(revision 163115)
+++ test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt	(working copy)
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
 
 # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
Index: test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
===================================================================
--- test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt	(revision 0)
+++ test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt	(revision 0)
@@ -0,0 +1,3 @@
+# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | grep "invalid instruction encoding"
+
+0xa0 0xf9 0xc0 0x0f
Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp
===================================================================
--- lib/Target/ARM/Disassembler/ARMDisassembler.cpp	(revision 163115)
+++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp	(working copy)
@@ -2701,6 +2701,8 @@
   unsigned align = fieldFromInstruction(Insn, 4, 1);
   unsigned size = fieldFromInstruction(Insn, 6, 2);
 
+  if (size == 0 && align == 1)
+    return MCDisassembler::Fail;
   align *= (1 << size);
 
   switch (Inst.getOpcode()) {
@@ -2831,6 +2833,8 @@
   unsigned align = fieldFromInstruction(Insn, 4, 1);
 
   if (size == 0x3) {
+    if (align == 0)
+      return MCDisassembler::Fail;
     size = 4;
     align = 16;
   } else {