<br><br><div class="gmail_quote">On 28 August 2012 15:31, Nadav Rotem <span dir="ltr"><<a href="mailto:nrotem@apple.com" target="_blank">nrotem@apple.com</a>></span> wrote:<br><blockquote style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid" class="gmail_quote">
Author: nadav<br>
Date: Tue Aug 28 05:01:43 2012<br>
New Revision: 162743<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=162743&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=162743&view=rev</a><br>
Log:<br>
<br>
Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.<br>
<br>
For example:<br>
%1 = lshr i32 %x, 2<br>
%2 = udiv i32 %1, 100<br></blockquote><div> </div><div>It is a right shift + div. Should not the log read as "[SU]div+[AL]shr" instead of "[SU]div+[AL]shl " ?</div><div> </div><div>Likewise for comments in file InstCombine/InstCombineMulDivRem.cpp </div>
<div> </div><div>+ // Udiv ((Lshl x, c1) , c2) -> x / (C1 * 1<<C2);</div><div>+ // Sdiv ((Ashl x, c1) , c2) -> x / (C1 * 1<<C2);</div><div> </div><div>I think they should be Lshr and Ashr respectively.</div>
<div> </div><div>-Anitha</div><div> </div><div> </div><div> </div><blockquote style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid" class="gmail_quote">
<br>
rdar://12182093<br>
<br>
<br>
<br>
Added:<br>
llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll<br>
Modified:<br>
llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp<br>
llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll<br>
<br>
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=162743&r1=162742&r2=162743&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=162743&r1=162742&r2=162743&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Tue Aug 28 05:01:43 2012<br>
@@ -462,6 +462,16 @@<br>
}<br>
}<br>
<br>
+ // Udiv ((Lshl x, c1) , c2) -> x / (C1 * 1<<C2);<br>
+ if (Constant *C = dyn_cast<Constant>(Op1)) {<br>
+ Value *X = 0, *C1 = 0;<br>
+ if (match(Op0, m_LShr(m_Value(X), m_Value(C1)))) {<br>
+ uint64_t NC = cast<ConstantInt>(C)->getZExtValue() *<br>
+ (1<< cast<ConstantInt>(C1)->getZExtValue());<br>
+ return BinaryOperator::CreateUDiv(X, ConstantInt::get(I.getType(), NC));<br>
+ }<br>
+ }<br>
+<br>
// X udiv (C1 << N), where C1 is "1<<C2" --> X >> (N+C2)<br>
{ const APInt *CI; Value *N;<br>
if (match(Op1, m_Shl(m_Power2(CI), m_Value(N))) ||<br>
@@ -533,6 +543,16 @@<br>
ConstantExpr::getNeg(RHS));<br>
}<br>
<br>
+ // Sdiv ((Ashl x, c1) , c2) -> x / (C1 * 1<<C2);<br>
+ if (Constant *C = dyn_cast<Constant>(Op1)) {<br>
+ Value *X = 0, *C1 = 0;<br>
+ if (match(Op0, m_AShr(m_Value(X), m_Value(C1)))) {<br>
+ uint64_t NC = cast<ConstantInt>(C)->getZExtValue() *<br>
+ (1<< cast<ConstantInt>(C1)->getZExtValue());<br>
+ return BinaryOperator::CreateSDiv(X, ConstantInt::get(I.getType(), NC));<br>
+ }<br>
+ }<br>
+<br>
// If the sign bits of both operands are zero (i.e. we can prove they are<br>
// unsigned inputs), turn this into a udiv.<br>
if (I.getType()->isIntegerTy()) {<br>
<br>
Added: llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll?rev=162743&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll?rev=162743&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll (added)<br>
+++ llvm/trunk/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll Tue Aug 28 05:01:43 2012<br>
@@ -0,0 +1,50 @@<br>
+; RUN: opt -S -instcombine < %s | FileCheck %s<br>
+<br>
+; rdar://12182093<br>
+<br>
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"<br>
+target triple = "x86_64-apple-macosx10.8.0"<br>
+<br>
+; CHECK: @udiv400<br>
+; CHECK: udiv i32 %x, 400<br>
+; CHECK: ret<br>
+define i32 @udiv400(i32 %x) {<br>
+entry:<br>
+ %div = lshr i32 %x, 2<br>
+ %div1 = udiv i32 %div, 100<br>
+ ret i32 %div1<br>
+}<br>
+<br>
+; CHECK: @sdiv400<br>
+; CHECK: sdiv i32 %x, 400<br>
+; CHECK: ret<br>
+define i32 @sdiv400(i32 %x) {<br>
+entry:<br>
+ %div = ashr i32 %x, 2<br>
+ %div1 = sdiv i32 %div, 100<br>
+ ret i32 %div1<br>
+}<br>
+<br>
+; CHECK: @udiv400_no<br>
+; CHECK: ashr<br>
+; CHECK: div<br>
+; CHECK: ret<br>
+define i32 @udiv400_no(i32 %x) {<br>
+entry:<br>
+ %div = ashr i32 %x, 2<br>
+ %div1 = udiv i32 %div, 100<br>
+ ret i32 %div1<br>
+}<br>
+<br>
+; CHECK: @sdiv400_yes<br>
+; CHECK: udiv i32 %x, 400<br>
+; CHECK: ret<br>
+define i32 @sdiv400_yes(i32 %x) {<br>
+entry:<br>
+ %div = lshr i32 %x, 2<br>
+ ; The sign bits of both operands are zero (i.e. we can prove they are<br>
+ ; unsigned inputs), turn this into a udiv.<br>
+ ; Next, optimize this just like sdiv.<br>
+ %div1 = sdiv i32 %div, 100<br>
+ ret i32 %div1<br>
+}<br>
<br>
Modified: llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll?rev=162743&r1=162742&r2=162743&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll?rev=162743&r1=162742&r2=162743&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll (original)<br>
+++ llvm/trunk/test/Transforms/InstCombine/udiv-simplify-bug-1.ll Tue Aug 28 05:01:43 2012<br>
@@ -6,9 +6,9 @@<br>
; The udiv instructions shouldn't be optimized away, and the<br>
; sext instructions should be optimized to zext.<br>
<br>
-define i64 @bar(i32 %x) nounwind {<br>
+define i64 @bar(i32 %x, i32 %g) nounwind {<br>
%y = lshr i32 %x, 30<br>
- %r = udiv i32 %y, 3<br>
+ %r = udiv i32 %y, %g<br>
%z = sext i32 %r to i64<br>
ret i64 %z<br>
}<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br><i style="font-family:times new roman,serif"><b> Anitha</b></i><br><br>