<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><br></div>This seems to be breaking the dragonegg bots:<div><span class="Apple-style-span" style="font-family: Times; "><pre style="font-family: 'Courier New', courier, monotype, monospace; "><span class="stderr" style="font-family: 'Courier New', courier, monotype, monospace; color: red; ">make[4]: *** [_divdc3.o] Error 1
../../../../gcc.src/libgcc/../gcc/libgcc2.c: In function ‘__divxc3’:
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 98
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 94
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 85
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 81
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 77
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 73
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 69
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 66
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 57
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 53
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 44
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 40
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 36
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 32
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 28
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 25
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 18
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 14
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 8
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: error: too many outgoing branch edges from bb 6
../../../../gcc.src/libgcc/../gcc/libgcc2.c:1944:1: internal compiler error: verify_flow_info failed
Please submit a full bug report,</span></pre></span><div><br></div><div>I am not sure how to fix this. Thanks,</div><div><br></div><div>Manman</div><div><br></div><div><div>On Jul 28, 2012, at 9:48 AM, Manman Ren wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: mren<br>Date: Sat Jul 28 11:48:01 2012<br>New Revision: 160919<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=160919&view=rev">http://llvm.org/viewvc/llvm-project?rev=160919&view=rev</a><br>Log:<br>X86 Peephole: fold loads to the source register operand if possible.<br><br>Machine CSE and other optimizations can remove instructions so folding<br>is possible at peephole while not possible at ISel.<br><br><a href="rdar://10554090">rdar://10554090</a> and <a href="rdar://11873276">rdar://11873276</a><br><br>Modified:<br> llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br> llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp<br> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br> llvm/trunk/lib/Target/X86/X86InstrInfo.h<br> llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll<br> llvm/trunk/test/CodeGen/X86/break-sse-dep.ll<br> llvm/trunk/test/CodeGen/X86/fold-load.ll<br> llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll<br> llvm/trunk/test/CodeGen/X86/sse-minmax.ll<br> llvm/trunk/test/CodeGen/X86/vec_compare.ll<br><br>Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)<br>+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sat Jul 28 11:48:01 2012<br>@@ -14,6 +14,7 @@<br> #ifndef LLVM_TARGET_TARGETINSTRINFO_H<br> #define LLVM_TARGET_TARGETINSTRINFO_H<br><br>+#include "llvm/ADT/SmallSet.h"<br> #include "llvm/MC/MCInstrInfo.h"<br> #include "llvm/CodeGen/DFAPacketizer.h"<br> #include "llvm/CodeGen/MachineFunction.h"<br>@@ -693,6 +694,16 @@<br> return false;<br> }<br><br>+ /// optimizeLoadInstr - Try to remove the load by folding it to a register<br>+ /// operand at the use. We fold the load instructions if and only if the<br>+ /// def and use are in the same BB.<br>+ virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,<br>+ const MachineRegisterInfo *MRI,<br>+ SmallSet<unsigned, 4> &FoldAsLoadDefRegs,<br>+ MachineInstr *&DefMI) const {<br>+ return 0;<br>+ }<br>+<br> /// FoldImmediate - 'Reg' is known to be defined by a move immediate<br> /// instruction, try to fold the immediate into the use instruction.<br> virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,<br><br>Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Sat Jul 28 11:48:01 2012<br>@@ -78,6 +78,7 @@<br> STATISTIC(NumBitcasts, "Number of bitcasts eliminated");<br> STATISTIC(NumCmps, "Number of compares eliminated");<br> STATISTIC(NumImmFold, "Number of move immediate folded");<br>+STATISTIC(NumLoadFold, "Number of loads folded");<br><br> namespace {<br> class PeepholeOptimizer : public MachineFunctionPass {<br>@@ -441,6 +442,7 @@<br> SmallPtrSet<MachineInstr*, 8> LocalMIs;<br> SmallSet<unsigned, 4> ImmDefRegs;<br> DenseMap<unsigned, MachineInstr*> ImmDefMIs;<br>+ SmallSet<unsigned, 4> FoldAsLoadDefRegs;<br> for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {<br> MachineBasicBlock *MBB = &*I;<br><br>@@ -448,6 +450,7 @@<br> LocalMIs.clear();<br> ImmDefRegs.clear();<br> ImmDefMIs.clear();<br>+ FoldAsLoadDefRegs.clear();<br><br> bool First = true;<br> MachineBasicBlock::iterator PMII;<br>@@ -489,6 +492,25 @@<br> Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);<br> }<br><br>+ MachineInstr *DefMI = 0;<br>+ MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI, FoldAsLoadDefRegs,<br>+ DefMI);<br>+ if (FoldMI) {<br>+ // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.<br>+ LocalMIs.erase(MI);<br>+ LocalMIs.erase(DefMI);<br>+ LocalMIs.insert(FoldMI);<br>+ MI->eraseFromParent();<br>+ DefMI->eraseFromParent();<br>+ ++NumLoadFold;<br>+<br>+ // MI is replaced with FoldMI.<br>+ Changed = true;<br>+ PMII = FoldMI;<br>+ MII = llvm::next(PMII);<br>+ continue;<br>+ }<br>+<br> First = false;<br> PMII = MII;<br> ++MII;<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jul 28 11:48:01 2012<br>@@ -3323,6 +3323,75 @@<br> return true;<br> }<br><br>+/// optimizeLoadInstr - Try to remove the load by folding it to a register<br>+/// operand at the use. We fold the load instructions if and only if the<br>+/// def and use are in the same BB.<br>+MachineInstr* X86InstrInfo::<br>+optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,<br>+ SmallSet<unsigned, 4> &FoldAsLoadDefRegs,<br>+ MachineInstr *&DefMI) const {<br>+ if (MI->mayStore() || MI->isCall())<br>+ // To be conservative, we don't fold the loads if there is a store in<br>+ // between.<br>+ FoldAsLoadDefRegs.clear();<br>+ // We only fold loads to a virtual register.<br>+ if (MI->canFoldAsLoad()) {<br>+ const MCInstrDesc &MCID = MI->getDesc();<br>+ if (MCID.getNumDefs() == 1) {<br>+ unsigned Reg = MI->getOperand(0).getReg();<br>+ // To reduce compilation time, we check MRI->hasOneUse when inserting<br>+ // loads. It should be checked when processing uses of the load, since<br>+ // uses can be removed during peephole.<br>+ if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->hasOneUse(Reg)) {<br>+ FoldAsLoadDefRegs.insert(Reg);<br>+ return 0;<br>+ }<br>+ }<br>+ }<br>+<br>+ // Collect information about virtual register operands of MI.<br>+ DenseMap<unsigned, unsigned> SrcVirtualRegToOp;<br>+ SmallSet<unsigned, 4> DstVirtualRegs;<br>+ for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {<br>+ MachineOperand &MO = MI->getOperand(i);<br>+ if (!MO.isReg())<br>+ continue;<br>+ unsigned Reg = MO.getReg();<br>+ if (!TargetRegisterInfo::isVirtualRegister(Reg))<br>+ continue;<br>+ if (MO.isDef())<br>+ DstVirtualRegs.insert(Reg);<br>+ else if (FoldAsLoadDefRegs.count(Reg)) {<br>+ // Only handle the case where Reg is used in a single src operand.<br>+ if (SrcVirtualRegToOp.find(Reg) != SrcVirtualRegToOp.end())<br>+ SrcVirtualRegToOp.erase(Reg);<br>+ else<br>+ SrcVirtualRegToOp.insert(std::make_pair(Reg, i));<br>+ }<br>+ }<br>+<br>+ for (DenseMap<unsigned, unsigned>::iterator SI = SrcVirtualRegToOp.begin(),<br>+ SE = SrcVirtualRegToOp.end(); SI != SE; SI++) {<br>+ // If the virtual register is updated by MI, we can't fold the load.<br>+ if (DstVirtualRegs.count(SI->first)) continue;<br>+<br>+ // Check whether we can fold the def into this operand.<br>+ DefMI = MRI->getVRegDef(SI->first);<br>+ assert(DefMI);<br>+ bool SawStore = false;<br>+ if (!DefMI->isSafeToMove(this, 0, SawStore))<br>+ continue;<br>+<br>+ SmallVector<unsigned, 8> Ops;<br>+ Ops.push_back(SI->second);<br>+ MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);<br>+ if (!FoldMI) continue;<br>+ FoldAsLoadDefRegs.erase(SI->first);<br>+ return FoldMI;<br>+ }<br>+ return 0;<br>+}<br>+<br> /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr<br> /// instruction with two undef reads of the register being defined. This is<br> /// used for mapping:<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Sat Jul 28 11:48:01 2012<br>@@ -387,6 +387,14 @@<br> unsigned SrcReg2, int CmpMask, int CmpValue,<br> const MachineRegisterInfo *MRI) const;<br><br>+ /// optimizeLoadInstr - Try to remove the load by folding it to a register<br>+ /// operand at the use. We fold the load instructions if and only if the<br>+ /// def and use are in the same BB.<br>+ virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,<br>+ const MachineRegisterInfo *MRI,<br>+ SmallSet<unsigned, 4> &FoldAsLoadDefRegs,<br>+ MachineInstr *&DefMI) const;<br>+<br> private:<br> MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,<br> MachineFunction::iterator &MFI,<br><br>Modified: llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/2012-05-19-avx2-store.ll Sat Jul 28 11:48:01 2012<br>@@ -3,8 +3,7 @@<br> define void @double_save(<4 x i32>* %Ap, <4 x i32>* %Bp, <8 x i32>* %P) nounwind ssp {<br> entry:<br> ; CHECK: vmovaps<br>- ; CHECK: vmovaps<br>- ; CHECK: vinsertf128<br>+ ; CHECK: vinsertf128 $1, ([[A0:%rdi|%rsi]]),<br> ; CHECK: vmovups<br> %A = load <4 x i32>* %Ap<br> %B = load <4 x i32>* %Bp<br><br>Modified: llvm/trunk/test/CodeGen/X86/break-sse-dep.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-sse-dep.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-sse-dep.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/break-sse-dep.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/break-sse-dep.ll Sat Jul 28 11:48:01 2012<br>@@ -34,8 +34,7 @@<br> define double @squirt(double* %x) nounwind {<br> entry:<br> ; CHECK: squirt:<br>-; CHECK: movsd ([[A0]]), %xmm0<br>-; CHECK: sqrtsd %xmm0, %xmm0<br>+; CHECK: sqrtsd ([[A0]]), %xmm0<br> %z = load double* %x<br> %t = call double @llvm.sqrt.f64(double %z)<br> ret double %t<br><br>Modified: llvm/trunk/test/CodeGen/X86/fold-load.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-load.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-load.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fold-load.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fold-load.ll Sat Jul 28 11:48:01 2012<br>@@ -45,3 +45,29 @@<br><br> }<br><br>+; <a href="rdar://10554090">rdar://10554090</a><br>+; xor in exit block will be CSE'ed and load will be folded to xor in entry.<br>+define i1 @test3(i32* %P, i32* %Q) nounwind {<br>+; CHECK: test3:<br>+; CHECK: movl 8(%esp), %eax<br>+; CHECK: xorl (%eax),<br>+; CHECK: j<br>+; CHECK-NOT: xor<br>+entry:<br>+ %0 = load i32* %P, align 4<br>+ %1 = load i32* %Q, align 4<br>+ %2 = xor i32 %0, %1<br>+ %3 = and i32 %2, 65535<br>+ %4 = icmp eq i32 %3, 0<br>+ br i1 %4, label %exit, label %land.end<br>+<br>+exit:<br>+ %shr.i.i19 = xor i32 %1, %0<br>+ %5 = and i32 %shr.i.i19, 2147418112<br>+ %6 = icmp eq i32 %5, 0<br>+ br label %land.end<br>+<br>+land.end:<br>+ %7 = phi i1 [ %6, %exit ], [ false, %entry ]<br>+ ret i1 %7<br>+}<br><br>Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll Sat Jul 28 11:48:01 2012<br>@@ -1,11 +1,14 @@<br>-; RUN: llc < %s -march=x86 -mattr=+sse2 > %t<br>-; RUN: grep pcmpeqd %t | count 1<br>-; RUN: grep xor %t | count 1<br>-; RUN: not grep LCP %t<br>+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s<br><br> define <2 x double> @foo() nounwind {<br> ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)<br>+; CHECK: foo:<br>+; CHECK: pcmpeqd %xmm{{[0-9]+}}, %xmm{{[0-9]+}}<br>+; CHECK-NEXT: ret<br> }<br> define <2 x double> @bar() nounwind {<br> ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)<br>+; CHECK: bar:<br>+; CHECK: xorps %xmm{{[0-9]+}}, %xmm{{[0-9]+}}<br>+; CHECK-NEXT: ret<br> }<br><br>Modified: llvm/trunk/test/CodeGen/X86/sse-minmax.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sse-minmax.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sse-minmax.ll Sat Jul 28 11:48:01 2012<br>@@ -137,16 +137,13 @@<br> }<br><br> ; CHECK: ogt_x:<br>-; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; CHECK-NEXT: maxsd %xmm1, %xmm0<br>+; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: ogt_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: maxsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: ogt_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: maxsd %xmm1, %xmm0<br>+; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @ogt_x(double %x) nounwind {<br> %c = fcmp ogt double %x, 0.000000e+00<br>@@ -155,16 +152,13 @@<br> }<br><br> ; CHECK: olt_x:<br>-; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; CHECK-NEXT: minsd %xmm1, %xmm0<br>+; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: olt_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: minsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: olt_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: minsd %xmm1, %xmm0<br>+; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @olt_x(double %x) nounwind {<br> %c = fcmp olt double %x, 0.000000e+00<br>@@ -217,12 +211,10 @@<br> ; CHECK: oge_x:<br> ; CHECK: ucomisd %xmm1, %xmm0<br> ; UNSAFE: oge_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: maxsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: oge_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: maxsd %xmm1, %xmm0<br>+; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @oge_x(double %x) nounwind {<br> %c = fcmp oge double %x, 0.000000e+00<br>@@ -233,12 +225,10 @@<br> ; CHECK: ole_x:<br> ; CHECK: ucomisd %xmm0, %xmm1<br> ; UNSAFE: ole_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: minsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: ole_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: minsd %xmm1, %xmm0<br>+; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @ole_x(double %x) nounwind {<br> %c = fcmp ole double %x, 0.000000e+00<br>@@ -411,12 +401,10 @@<br> ; CHECK: ugt_x:<br> ; CHECK: ucomisd %xmm0, %xmm1<br> ; UNSAFE: ugt_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: maxsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: ugt_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: maxsd %xmm1, %xmm0<br>+; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @ugt_x(double %x) nounwind {<br> %c = fcmp ugt double %x, 0.000000e+00<br>@@ -427,12 +415,10 @@<br> ; CHECK: ult_x:<br> ; CHECK: ucomisd %xmm1, %xmm0<br> ; UNSAFE: ult_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: minsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: ult_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: minsd %xmm1, %xmm0<br>+; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @ult_x(double %x) nounwind {<br> %c = fcmp ult double %x, 0.000000e+00<br>@@ -482,12 +468,10 @@<br> ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: uge_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: maxsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: uge_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: maxsd %xmm1, %xmm0<br>+; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @uge_x(double %x) nounwind {<br> %c = fcmp uge double %x, 0.000000e+00<br>@@ -501,12 +485,10 @@<br> ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: ule_x:<br>-; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; UNSAFE-NEXT: minsd %xmm1, %xmm0<br>+; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; UNSAFE-NEXT: ret<br> ; FINITE: ule_x:<br>-; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; FINITE-NEXT: minsd %xmm1, %xmm0<br>+; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; FINITE-NEXT: ret<br> define double @ule_x(double %x) nounwind {<br> %c = fcmp ule double %x, 0.000000e+00<br>@@ -515,8 +497,7 @@<br> }<br><br> ; CHECK: uge_inverse_x:<br>-; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; CHECK-NEXT: minsd %xmm1, %xmm0<br>+; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: uge_inverse_x:<br> ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>@@ -535,8 +516,7 @@<br> }<br><br> ; CHECK: ule_inverse_x:<br>-; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br>-; CHECK-NEXT: maxsd %xmm1, %xmm0<br>+; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0<br> ; CHECK-NEXT: ret<br> ; UNSAFE: ule_inverse_x:<br> ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/vec_compare.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare.ll?rev=160919&r1=160918&r2=160919&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare.ll?rev=160919&r1=160918&r2=160919&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vec_compare.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vec_compare.ll Sat Jul 28 11:48:01 2012<br>@@ -14,8 +14,8 @@<br> define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {<br> ; CHECK: test2:<br> ; CHECK: pcmp<br>-; CHECK: pcmp<br>-; CHECK: pxor<br>+; CHECK: pxor LCP<br>+; CHECK: movdqa<br> ; CHECK: ret<br> <span class="Apple-tab-span" style="white-space:pre"> </span>%C = icmp sge <4 x i32> %A, %B<br> %D = sext <4 x i1> %C to <4 x i32><br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>