<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div>Richard,</div>This appears to be causing failures on our internal builders with the following warnings:<div><br></div><div><pre style="font-family: 'Courier New', courier, monotype; "><span class="stdout" style="font-family: 'Courier New', courier, monotype; color: black; ">******************** TEST 'LLVM :: MC/Disassembler/ARM/neon.txt' FAILED ********************Script:
--
0xa4 0x0d 0xa3 0xf4
^
llvm/test/MC/Disassembler/ARM/neon.txt:1898:10: error: expected string not found in input
# CHECK: vmovvs r2, lr, s29, s30
^
<stdin>:897:2: note: scanning from here
stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^
^
<stdin>:897:11: note: possible intended match here
stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^
^
--
********************
</span></pre><div><font class="Apple-style-span" face="'Courier New', courier, monotype"> </font>Chad</div></div><div><div><div><br></div><div>On Jul 9, 2012, at 9:41 AM, Richard Barton wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: rbarton<br>Date: Mon Jul 9 11:41:33 2012<br>New Revision: 159938<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=159938&view=rev">http://llvm.org/viewvc/llvm-project?rev=159938&view=rev</a><br>Log:<br>Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)<br><br>Modified:<br> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br> llvm/trunk/test/MC/ARM/simple-fp-encoding.s<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=159938&r1=159937&r2=159938&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=159938&r1=159937&r2=159938&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Jul 9 11:41:33 2012<br>@@ -567,8 +567,8 @@<br> bits<4> Rt2;<br><br> // Encode instruction operands.<br>- let Inst{3-0} = src1{3-0};<br>- let Inst{5} = src1{4};<br>+ let Inst{3-0} = src1{4-1};<br>+ let Inst{5} = src1{0};<br> let Inst{15-12} = Rt;<br> let Inst{19-16} = Rt2;<br><br>@@ -617,8 +617,8 @@<br> bits<4> src2;<br><br> // Encode instruction operands.<br>- let Inst{3-0} = dst1{3-0};<br>- let Inst{5} = dst1{4};<br>+ let Inst{3-0} = dst1{4-1};<br>+ let Inst{5} = dst1{0};<br> let Inst{15-12} = src1;<br> let Inst{19-16} = src2;<br><br><br>Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=159938&r1=159937&r2=159938&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=159938&r1=159937&r2=159938&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Jul 9 11:41:33 2012<br>@@ -4198,9 +4198,9 @@<br> DecodeStatus S = MCDisassembler::Success;<br> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br>- unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>+ unsigned Rm = fieldFromInstruction32(Insn, 5, 1);<br> unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>- Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br>+ Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;<br><br> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br> S = MCDisassembler::SoftFail;<br>@@ -4224,9 +4224,9 @@<br> DecodeStatus S = MCDisassembler::Success;<br> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br>- unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>+ unsigned Rm = fieldFromInstruction32(Insn, 5, 1);<br> unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>- Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br>+ Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;<br><br> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br> S = MCDisassembler::SoftFail;<br><br>Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=159938&r1=159937&r2=159938&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=159938&r1=159937&r2=159938&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)<br>+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Jul 9 11:41:33 2012<br>@@ -196,6 +196,27 @@<br> @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]<br> vmov r0, r1, d16<br><br>+@ Between two single precision registers and two core registers<br>+ vmov s3, s4, r1, r2<br>+ vmov s2, s3, r1, r2<br>+ vmov r1, r2, s3, s4<br>+ vmov r1, r2, s2, s3<br>+@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec]<br>+@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec]<br>+@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec]<br>+@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec]<br>+<br>+@ Between one double precision register and two core registers<br>+ vmov d15, r1, r2 <br>+ vmov d16, r1, r2<br>+ vmov r1, r2, d15<br>+ vmov r1, r2, d16<br>+@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec]<br>+@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec]<br>+@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec]<br>+@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec]<br>+<br>+<br> @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]<br> @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]<br> @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>