<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Richard,<div>Looks like this isn't quite fixed; the register names are not matching.</div><div><span class="Apple-style-span" style="font-family: 'Courier New', courier, monotype; white-space: pre; "><br></span></div><div><span class="Apple-style-span" style="font-family: 'Courier New', courier, monotype; white-space: pre; ">--</span></div><div><span class="Apple-style-span" style="font-family: Times; "><pre style="font-family: 'Courier New', courier, monotype; "><span class="stdout" style="font-family: 'Courier New', courier, monotype; color: black; ">llvm/test/MC/Disassembler/ARM/neon.txt:1898:10: error: expected string not found in input
# CHECK: vmovvs r2, lr, s29, s30
^
<stdin>:897:2: note: scanning from here
vmovvs r2, lr, s27, s28
^
--</span></pre></span><div> Chad</div><div><br></div><div><br></div><div><div>On Jul 9, 2012, at 11:23 AM, Chad Rosier wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div><br>On Jul 9, 2012, at 11:22 AM, Richard Barton wrote:<br><br><blockquote type="cite">Hi Chad<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">My change completely broke disassembling the VMOV Rt, Rt2, Sm, Sm+1 instruction.<br></blockquote><blockquote type="cite">I must not have run the full test suite over it - must do better!<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Have committed a fix: r159945. Sorry for the breakage.<br></blockquote><br>Thanks for the quick fix!<br><br> Chad<br><br><blockquote type="cite">Rich<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><blockquote type="cite">-----Original Message-----<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">From: Chad Rosier [mailto:mcrosier@apple.com]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">Sent: 09 July 2012 19:02<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">To: Richard Barton<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">Cc: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">Subject: Re: [llvm-commits] [llvm] r159938 - in /llvm/trunk:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">test/MC/ARM/simple-fp-encoding.s<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">Richard,<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">This appears to be causing failures on our internal builders with the<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">following warnings:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">******************** TEST 'LLVM :: MC/Disassembler/ARM/neon.txt' FAILED<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">********************Script:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">--<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">0xa4 0x0d 0xa3 0xf4<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"> ^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">llvm/test/MC/Disassembler/ARM/neon.txt:1898:10: error: expected string not<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">found in input<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"># CHECK: vmovvs r2, lr, s29, s30<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"> ^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><stdin>:897:2: note: scanning from here<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><stdin>:897:11: note: possible intended match here<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"> ^<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">--<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">********************<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">Chad<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">On Jul 9, 2012, at 9:41 AM, Richard Barton wrote:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Author: rbarton<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Date: Mon Jul 9 11:41:33 2012<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>New Revision: 159938<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=159938&view=rev">http://llvm.org/viewvc/llvm-project?rev=159938&view=rev</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Log:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Fix instruction description of VMOV (between two ARM core registers and<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">two single-precision resiters)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Modified:<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> llvm/trunk/test/MC/ARM/simple-fp-encoding.s<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>URL: <a href="http://llvm.org/viewvc/llvm-">http://llvm.org/viewvc/llvm-</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=159938&r1=159937&r2=15993<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">8&view=diff<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>========================================================================<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">======<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Jul 9 11:41:33 2012<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@@ -567,8 +567,8 @@<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> bits<4> Rt2;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> // Encode instruction operands.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- let Inst{3-0} = src1{3-0};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- let Inst{5} = src1{4};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ let Inst{3-0} = src1{4-1};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ let Inst{5} = src1{0};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> let Inst{15-12} = Rt;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> let Inst{19-16} = Rt2;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@@ -617,8 +617,8 @@<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> bits<4> src2;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> // Encode instruction operands.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- let Inst{3-0} = dst1{3-0};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- let Inst{5} = dst1{4};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ let Inst{3-0} = dst1{4-1};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ let Inst{5} = dst1{0};<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> let Inst{15-12} = src1;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> let Inst{19-16} = src2;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>URL: <a href="http://llvm.org/viewvc/llvm-">http://llvm.org/viewvc/llvm-</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=159938&<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">r1=159937&r2=159938&view=diff<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>========================================================================<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">======<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">(original)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Jul<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">9 11:41:33 2012<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@@ -4198,9 +4198,9 @@<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> DecodeStatus S = MCDisassembler::Success;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ unsigned Rm = fieldFromInstruction32(Insn, 5, 1);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> S = MCDisassembler::SoftFail;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@@ -4224,9 +4224,9 @@<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> DecodeStatus S = MCDisassembler::Success;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ unsigned Rm = fieldFromInstruction32(Insn, 5, 1);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>- Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> S = MCDisassembler::SoftFail;<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">fp-encoding.s?rev=159938&r1=159937&r2=159938&view=diff<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>========================================================================<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">======<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Jul 9 11:41:33 2012<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@@ -196,6 +196,27 @@<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span> vmov r0, r1, d16<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ Between two single precision registers and two core registers<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov s3, s4, r1, r2<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov s2, s3, r1, r2<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov r1, r2, s3, s4<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov r1, r2, s2, s3<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ Between one double precision register and two core registers<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov d15, r1, r2<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov d16, r1, r2<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov r1, r2, d15<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+ vmov r1, r2, d16<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>+<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>@ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>_______________________________________________<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>llvm-commits mailing list<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><br></div></blockquote></div><br></div></body></html>