<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div></div><div><br></div><div><blockquote type="cite"><div><font class="Apple-style-span" color="#000000"><br></font></div><div><font class="Apple-style-span" color="#000000"><br></font>-----Original Message-----<br>From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:llvm-commits-bounces@cs.uiuc.edu] On Behalf Of Manman Ren<br>Sent: Saturday, June 23, 2012 01:12<br>To: Commit Messages and Patches for LLVM<br>Subject: [llvm-commits] [PATCH] X86: Add support for GATHER intrinsics of X86 AVX2, please review<br><br><br>Support the following intrinsics:<br> _mm_mask_i32gather_pd, _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd<br> _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps, _mm256_mask_i32gather_ps<br> _mm_mask_i64gather_ps, _mm256_mask_i64gather_ps<br><br>There are two places which I am not sure about:<br>1> Is a customized ISel needed for GATHER?<br> I can't figure out how to select the address operands for GATHER intrinsics<br> in a .td file, given that index and scale are passed in as parameters.<br> gather(<2 x double> %a0, i8* %base, <2 x i64> %idx, <2 x double> %mask, i8 scale) <br><br>2> Is there a better way to modify disassembler to handle VSIB addressing mode?<br> The existing disassembler assumes index register is encoded for SIB only.<br> However VSIB has a different mapping for the index registers.<br> For example: index field of 100 means VR4 or VR12 for VSIB, and it means<br> no index register for SIB.<br> We don't know whether it is VSIB or SIB before the instruction ID is decoded.<br> It looks to me that X86::VGATHER is not exposed to readSIB in X86DisassemblerDecoder.c<br> The attached patch checks whether it is VSIB during translation and if yes,<br> it will update index register to the correct value according to VSIB.<br><br>File modified:<br>test/MC/X86/x86_64-avx-encoding.s<br>test/MC/Disassembler/X86/simple-tests.txt<br>test/CodeGen/X86/avx2-intrinsics-x86.ll<br>include/llvm/IntrinsicsX86.td<br>utils/TableGen/EDEmitter.cpp<br>utils/TableGen/X86RecognizableInstr.cpp<br>lib/Target/X86/X86InstrInfo.td<br>lib/Target/X86/AsmParser/X86AsmParser.cpp<br>lib/Target/X86/X86ISelDAGToDAG.cpp<br>lib/Target/X86/X86InstrSSE.td<br>lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>lib/Target/X86/Disassembler/X86DisassemblerDecoder.h<br>lib/Target/X86/Disassembler/X86Disassembler.cpp<br><br>Comments are appreciated.<br><br>Thanks,<br>Manman<br>---------------------------------------------------------------------<br>Intel Israel (74) Limited<br><br>This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.<br><br></div></blockquote></div><br></body></html>